Product category:
Design and Development Software
News Release from: Synopsys | Subject: DesignWare System Level Library
Edited by the Electronicstalk Editorial
Team on 18 September 2007
Library suits virtual platform assembly
All DesignWare System Level Library models are written in SystemC and work in IEEE1666 (SystemC)-compliant simulation environments, making them tool-independent.
Synopsys has released the DesignWare System Level Library, providing high-performance SystemC transaction-level simulation models (TLMs) for assembling virtual platforms, including instruction set simulators (ISS), and TLMs of Synopsys' DesignWare cores and AMBA components All DesignWare System Level Library models are written in SystemC and work in IEEE1666 (SystemC)-compliant simulation environments, making them tool-independent
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Transaction-level models are the basic building blocks required to build virtual platforms for early hardware/software co-design, architectural exploration and system verification.
Virtual platforms are fast, full-function simulation models of the hardware that enable development and integration of software months before hardware is available.
"The largest ESL market today is the software virtual prototype, and it could also be the fastest growing but for two issues", said Gary Smith, Chief Analyst of Gary Smith EDA.
"First is a standard modelling language and second is a critical mass of models using that language".
"Synopsys' introduction of the SystemC based transaction level models in their DesignWare System Level Library addresses both of these".
The DesignWare System Level Library features more than 50 TLMs, including high-performance microprocessor models and models of DesignWare standards-based connectivity IP such as USB 2.0 HS OTG, SATA AHCI and AMBA components.
Pre-assembled models of complete platforms are also included, and can be used as reference designs for driver development or as a starting point for building larger virtual platforms.
"One of the obstacles to faster adoption of electronic system level development methodologies has been the lack of fast transaction-level models", said Joachim Kunkel, Vice President and General Manager of Synopsys' solutions group.
"The availability of transaction level models for our widely used DesignWare IP as well as third-party IP can significantly shorten the time required to build virtual platforms for pre-silicon hardware/software integration projects, architectural exploration and system-level verification".
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