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Product category: Design and Development Software
News Release from: Synopsys | Subject: DesignWare USB 2.0 nanoPHY
Edited by the Electronicstalk Editorial Team on 24 September 2007

US systems receive new certification

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The DesignWare PHY IP for PCI Express offers a number of dedicated lane configurations from x1 to x8 that support both wire bond and flip chip packages.

Synopsys' DesignWare USB 2.0 nanoPHY IP has achieved USB logo certification and its PCI Express (PCIe) PHY IP has passed compliance testing when implemented in SMIC's 130nm G process technology The DesignWare USB 2.0 nanoPHY IP provides a small area and low power

The PHY's tunability enables a high yield and robust interoperability by allowing designers to quickly adjust for process variation and system parasitics.

The DesignWare USB 2.0 nanoPHY is part of a solution for USB protocol implementation including OTG digital controllers, host controllers and verification IP.

Compliant with PCI Express 1.1, the DesignWare PHY IP for PCI Express offers low power consumption.

Its built- in diagnostics engine and ATE test vectors enable at-speed production testing of the PHYs.

Additionally, the DesignWare PHY IP for PCI Express offers a number of dedicated lane configurations from x1 to x8 that support both wire bond and flip chip packages.

The DesignWare PHY IP for PCI Express is part of a comprehensive silicon proven PCIe solution which includes endpoint, dual-mode, root complex and switch IP as well as verification IP.

"Synopsys provides our customers with industry leading USB and PCIe IP that offers a wide range of advanced features combined with excellent technical support", said Paul OuYang, SMIC Marketing and Sales.

"Combining Synopsys' certified, silicon-proven IP with our manufacturing process technology enables designers to achieve their time to market goals, while providing a fast, low-risk path to volume production".

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