Product category:
Intellectual Property Cores
News Release from: Synopsys | Subject: DesignWare DDR Protocol Controller IP
Edited by the Electronicstalk Editorial
Team on 31 January 2008
IP integration provides bandwidth for
digital TV
The integration of the DesignWare DDR Protocol Controller IP and the Arteris NoC solution provide designers with memory traffic bandwidth and quality of service.
Synopsys' DesignWare DDR Protocol Controller IP has been integrated with the Arteris network-on-chip (NoC) solution for complex system-on-chips (SoCs) This combination delivers reliable, high-speed, on-chip connectivity with low latency to external DDR2 and DDR3 SDRAM memory for advanced systems
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Applications include digital TVs, set-top boxes, telecom and storage require high-performance data traffic between the various processor subsystems and on-chip peripherals that extend to off-chip DDR SDRAM memory.
The integration of the silicon-proven DesignWare DDR Protocol Controller IP and the silicon-proven Arteris NoC solution addresses these challenges by providing designers with the necessary memory traffic bandwidth and quality of service.
"We have worked closely with Arteris to integrate the Synopsys DesignWare DDR Protocol Controller IP into the Arteris memory scheduler and NoC solution", said Joachim Kunkel, Vice President and General Manager of the Solutions Group at Synopsys.
"Arteris' customers now have access to high-quality, pre-verified DDR Memory Controller subsystem IP, shortening design time and lowering risk".
The Arteris NoC is capable of operating at frequencies exceeding 750MHz in a 65nm process and offers link widths from 32 to 128bit for high system bandwidth.
The NoC typically uses fewer top-level wires compared to a traditional on-chip bus fabric.
The highly configurable DesignWare DDR Protocol Controller IP supports the latest DDR2 and DDR3 memory devices operating at up to 1600Mbit/s.
Synopsys provides a complete, silicon-proven IP solution comprised of a digital controller core, mixed-signal PHYs targeting today's foundries and process nodes and verification IP for subsystem and system-level verification.
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