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News Release from: Synopsys | Subject: DesignWare USB
Edited by the Electronicstalk Editorial
Team on 05 February 2008
Sleep state cuts USB power consumption
The DesignWare USB LPM IP digital controller and PHY IP implement a new power sleep state to reduce power consumption.
Synopsys has added support for the USB 2.0 Link Power Management (LPM) and High Speed Inter-Chip (HSIC) standards to its DesignWare USB IP product line The new DesignWare USB LPM and HSIC digital controller and PHY IP reduce power consumption and area for USB-enabled chips
This article was originally published on Electronicstalk on 17 Nov 2003 at 8.00am (UK)
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IP certified for Hi-Speed USB
The DesignWare USB 2.0 Multiport Host and PHY have become the first host IP building blocks to achieve Hi-Speed certification from the USB Implementers Forum.
USB cores extend down to TSMC 90nm process
The latest additions to the DesignWare portfolio are a USB 2.0 On-The-Go PHY core for TSMC's 90, 130 and 180nm processes as well as an extension of the Hi-Speed USB 2.0 PHY core to the 90nm process.
The DesignWare USB LPM IP digital controller and PHY IP implement a new power sleep state to reduce power consumption.
The USB LPM IP can provide faster suspend and resume times that are measured in microseconds instead of the milliseconds required by the existing USB 2.0 specification.
This allows devices to save power by more frequently turning off the USB connection while idle.
Further reading
Interface IP eases USB 2.0 integration
New USB 2.0 PHY IP is tailored specifically for low power consumption, small area and high yield.
USB 2.0 IP runs on TSMC's 90nm LP process
The DesignWare USB 2.0 nanoPHY IP is Synopsys' next-generation USB 2.0 mixed-signal PHY targeting low-power and consumer applications.
The DesignWare USB LPM IP is designed to further reduce power consumption over the existing low power DesignWare USB 2.0 IP architecture.
The current DesignWare Hi-Speed USB On-the-Go digital controller IP implements multiple power domains, allowing nearly the entire core to be completely turned off while idle.
This maximises battery life with reduced leakage power by 95% compared to solutions that do not employ multiple power domains.
The DesignWare HSIC digital controller and PHY IP eliminates USB cables and connectors and simplifies the connection to two wires for high-speed chip to chip communication operating up to 480Mbit/s.
Unlike other USB HSIC PHY offerings, the DesignWare USB HSIC IP is the industry's only IP solution consisting of integrated high-speed digital and analogue blocks, PLL and I/O pads, which are delivered as GDSII for advanced foundry processes.
This can save designers significant time, cost and the risk of acquiring and integrating the IP separately.
By eliminating the need for 3.3V signaling and 5V short protection logic, the DesignWare USB HSIC PHY offers up to 50% lower power and 75% smaller area than traditional USB 2.0 PHYs.
The DesignWare USB HSIC IP remains fully compatible with existing USB software stacks, allowing designers to lower system costs, shorten design time and improve productivity by reusing existing USB interfaces, drivers and firmware.
The DesignWare USB HSIC digital controller, which is compliant with HSIC signaling, supports high-speed USB 2.0 data transfers up to 480Mbit/s.
The USB HSIC IP solution is suitable for applications such as 3G/4G handsets, smartphones, set top boxes and mobile internet devices.
Jeff Ravencraft, USB-IF President said "This solution enables manufacturers to integrate USB IP into mobile applications for higher bandwidth chip to chip connectivity with enhanced battery life and ultimately pass the cost savings to their customers".
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