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Design and Development Software
News Release from: Synopsys | Subject: Synopsys Eclypse Low Power Solution
Edited by the Electronicstalk Editorial
Team on 26 February 2008
Tool suite eases chip development
The Synopsys Eclypse Low Power Solution enables design teams to adopt advanced low power techniques while boosting productivity and reducing risk.
The Synopsys Eclypse Low Power Solution is a suite of proven system-level, verification, implementation and signoff tools, intellectual property (IP), methodologies and services for low-power chip development The Eclypse solution aligns Synopsys' proven offerings into a streamlined, easy to use low power workflow that encompasses each phase of the design process
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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As a result, the Eclypse solution enables design teams to adopt advanced low power techniques while boosting productivity, reducing risk and ultimately delivering high-quality silicon in an effort to meet or beat power, area, speed and yield objectives.
To educate customers on the benefits of the Eclypse solution, Synopsys will host a series of low power seminars around the world.
Advanced low power design techniques, such as MTCMOS power gating, multivoltage and dynamic voltage and frequency scaling (DVFS), force a major shift in how engineers create and verify chips.
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These techniques can dramatically reduce power consumption in deep submicron chips but have traditionally required ad hoc, time consuming, risk prone and manual verification and implementation approaches.
The Eclypse Low Power Solution combines a wide array of advanced techniques, methodologies, standards and automation to simplify advanced low power design and verification.
Enhanced clock gating and low power clock-tree synthesis allow designers to optimise their clock structures for low power while also achieving required skew and timing goals.
Multithreshold leakage optimisation, which constrains the ratio of Vt, options used, provides optimal leakage power recovery independent of a design's process corners.
Enhanced automation for power switch insertion and optimisation enables power planning exploration and "what-if" analysis using IR drop and area constraints.
The Eclypse solution supports the industry-standard Unified Power Format (UPF) language, which is used to capture low power design requirements.
The system includes MVRC and VCS with MVSIM, key components of the Discovery Verification Platform and Design Compiler, Power Compiler, IC Compiler, DFT MAX, Formality and PrimeTime, key components of the Galaxy Design Platform.
Completing the solution are additional tools for low power design, including Innovator, HSPICE, HSIM, NanoSim, TetraMAX and PrimeRail, as well as DesignWare IP and Synopsys Professional Services.
The Eclypse solution supports open methodologies, including those described in the "Low Power Methodology Manual", co-authored by Synopsys and ARM.
Synopsys will conduct a series of Eclypse Low Power Seminars in which ARM will participate.
These seminars are designed to help chip development teams understand how they can employ low power design techniques with the Eclypse solution.
The seminars will include an overview of the Eclypse solution and detail key elements of an automated low-power design workflow.
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