Product category:
Design and Development Software
News Release from: Synopsys | Subject: IC Compiler 2007.12
Edited by the Electronicstalk Editorial
Team on 04 March 2008
Hierarchical system tackles large
designs
The IC Compiler 2007.12 hierarchical design flow enables a concurrent methodology where planning occurs in tandem with implementation, delivering faster time to tapeout.
Synopsys has released t the industry's first concurrent hierarchical design system as part of the IC Compiler 2007.12 release As designers migrate to smaller geometries, on-chip integration increases and design sizes mushroom
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Current generation design tools rely on a "plan then implement" flow which begins to break down in the face of these large designs, which often include multiple modes and multiple voltage domains.
The IC Compiler 2007.12 release transcends these flows by enabling a concurrent methodology where planning occurs in tandem with implementation, delivering faster time to tapeout.
The 2007.12 release also includes advances in clock tree synthesis technology that improves clock skew and lowers power dissipation.
The new release directly boosts designer productivity by providing a 30% reduction in total run time.
"We are enabling fundamentally new usage models with concurrent hierarchical design which can deliver significant productivity advantages for customers currently using a sequential process of design planning followed by implementation", said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.
"With this foundation now in place, Synopsys is positioned very well for extending this capability to the next phase of automatic minimum-die hierarchy generation, making hierarchical design dramatically easier".
Historically, "plan then implement" flows have worked well for simple designs.
However, for complex designs, these flows lead to late discovery of physical design issues, resulting in overdesign and often requiring iterations back to the early planning stages.
For these complex designs, a concurrent flow that seamlessly blends planning and implementation tasks and offers an integrated environment with a single timer and high correlation with sign off becomes increasingly critical.
IC Compiler 2007.12 provides hand craft quality macro placement, intelligent power network support and MinChip technology for automatic die size reduction, all on a single timer foundation that enables faster time to closure with higher quality of results.
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