Product category:
Design and Development Software
News Release from: Synopsys | Subject: Design Compiler Graphical synthesis product
Edited by the Electronicstalk Editorial
Team on 01 April 2008
Software avoids SoC traffic jams
The ability to predict, visualise and alleviate routing problems prior to physical implementation substantially reduces iterations between synthesis and place and route.
Synopsys has released its Design Compiler Graphical synthesis product, which shortens implementation time for system-on-chip (SoC) devices by helping RTL designers avoid wire routing congestion problems Design Compiler Graphical predicts circuit congestion "hot spots" early in the design flow, provides designers with visualisation of the congested circuit regions and performs synthesis optimisations to minimise congestion in these areas
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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The ability to predict, visualise and alleviate routing problems prior to physical implementation substantially reduces iterations between synthesis and place and route and can significantly lower project time, effort and cost.
"Topographical technology in Design Compiler has already delivered a boost in our designers' productivity", said Shahar Even-Zur, Physical Design Team Leader at Dune Networks.
"We expect another significant reduction in design implementation time using the new Design Compiler Graphical product after having verified that it automatically reduces routing congestion during RTL synthesis".
Designers worldwide have achieved rapid design closure using Design Compiler topographical technology to ensure tight timing, area and power correlation with IC Compiler physical implementation results.
However, even if a design meets all the performance specifications, congestion can be severe enough to make it very difficult to successfully route the design, leading to longer design cycles and more iterations between synthesis and place-and-route.
Synopsys' Design Compiler Graphical product circumvents these iterations, which can be especially lengthy and painstaking for very large designs.
It provides congestion reports and visualisation to assist designers in identifying congested regions in a circuit.
It employs optimisation techniques to synthesise a design with significantly less congestion, thereby creating a better starting point for physical design.
The ability to first estimate and then prevent routing congestion problems early in the design phase produces a more predictable, streamlined design flow from RTL synthesis through physical implementation, shaving weeks off project schedules.
Design Compiler Graphical is available as an add on to DC Ultra.
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