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Product category: Intellectual Property Cores
News Release from: Synopsys | Subject: DesignWare USB 2.0
Edited by the Electronicstalk Editorial Team on 18 April 2008

USB2.0 IP receives PHY certification

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Synopsys' DesignWare USB 2.0 nanoPHY uses half the power and die area of previous USB PHY IP solutions and enables faster time to market with reduced risk.

Synopsys' DesignWare USB 2.0 nanoPHY is the first 45nm USB 2.0 PHY intellectual property (IP) to successfully pass the USB Implementers Forum Hi-Speed USB PHY certification The nanoPHY mixed-signal IP, now available in the 45nm process node, uses half the power and die area of previous USB PHY IP solutions and enables faster time to market with reduced risk

The DesignWare USB 2.0 nanoPHY IP suits a broad range of high-volume, mobile and consumer applications where the key requirements include minimal area and low power consumption.

This IP addresses these key requirements by implementing an architecture that provides a highly effective combination of small area, low power consumption and minimal leakage.

In addition, the DesignWare USB 2.0 nanoPHY IP has built-in tuning circuits that enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations without the need to modify the existing design.

This feature allows designers to increase yield and minimise the cost of expensive silicon re-spins.

The DesignWare USB 2.0 nanoPHY is part of the complete USB 2.0 IP solution from Synopsys, which includes the USB 2.0 digital controllers, PHY and verification IP.

Synopsys offers a portfolio of USB IP for 180, 130, 90, 65 and 45nm process technologies.

The DesignWare USB IP products have been certified in hundreds of USB applications and are shipping in high-volume production.

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