Product category:
Design and Development Software
News Release from: Synopsys | Subject: VMM methodology
Edited by the Electronicstalk Editorial
Team on 09 May 2008
VMM methodology speeds I/O design
Pairing the VMM methodology with the VCS tool enabled NextIO to efficiently build highly accurate system-level and unit-level simulation environments that quickly identify design bugs.
NextIO has standardised on the VMM methodology and Synopsys' VCS functional verification product to accelerate the SystemVerilog-based verification of its newest I/O virtualisation chip design Pairing the VMM methodology with the VCS tool enabled NextIO to efficiently build highly accurate system-level and unit-level simulation environments that quickly identify design bugs
This article was originally published on Electronicstalk on 8 Oct 2007 at 8.00am (UK)
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This complete verification environment enabled NextIO to achieve first-pass functional silicon success.
Rich Warwick, Vice President of Engineering and Operations at NextIO said "The VMM methodology and Synopsys' implementation of the VMM base classes helped us structure a verification environment that used the full power of SystemVerilog".
"By standardising all of our testbenches on VMM, we have been able to reduce development time by 50%".
"VMM solved every verification challenge we faced".
NextIO was able to create its own base classes derived from the VMM base classes that they are now able to extend on a project-by-project basis.
This flexible approach allows NextIO to quickly assemble both unit-level and chip-level testbenches in a standardised fashion.
This standardisation significantly reduces the learning curve for NextIO's designers and verification engineers when new chips are developed, shortening the development schedules of future designs.
Subsequent designs will require a certain amount of new, design-specific code, but NextIO expects to re-use 80to 90% of the environment they architected for their second generation chip".
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