Product category:
Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 13 May 2008
Verification donation eases
interoperability
Synopsys' donation addresses customers' need for a modular, scalable and re-usable design methodology standard, while enabling them to more easily develop and share complex verification environments.
Synopsys is donating its complete implementation of the VMM verification methodology for SystemVerilog, including the VMM Standard Library and VMM Applications, to Accellera to enable verification interoperability standardisation Accellera has accepted the donation so the recently formed Accellera Verification IP (VIP) Technical Subcommittee can use it for standardisation activities
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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The VMM methodology, originally defined in the Verification Methodology Manual for SystemVerilog, has been used successfully by hundreds of verification teams since its introduction in 2005.
Synopsys' donation to Accellera addresses customers' need for a modular, scalable and re-usable design methodology standard, while enabling them to more easily develop and share complex verification environments.
"Accellera's newest standardisation activity will promote interoperability among vendors' and users' verification methodologies", said Shrenik Mehta, Accellera chair.
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"The donation of Synopsys' VMM implementation provides the technical subcommittee with established technology to meet their objectives".
"The enormous investment in the VMM methodology made by Synopsys, its partners and customers over the past four years has helped design teams around the world take full advantage of SystemVerilog", said Manoj Gandhi, Senior Vice President and General Manager of the Verification Group at Synopsys.
"Accellera's acceptance of Synopsys' donation of its complete implementation of the VMM methodology enables Accellera to leverage this investment to create a single, unified standard that will accelerate the pace of innovation".
A complete methodology requires more than just a standard base class library.
It requires applications that provide high-level functions to further increase productivity, macros and utilities to cut down testbench creation time and clear documentation and examples to shorten the learning curve.
Synopsys has donated its complete implementation of the VMM methodology, which includes: the VMM Standard Library; the VMM Register Abstraction Layer application; the VMM Re-usable Environment Composition application; the VMM Memory Allocation Manager application; the VMM Hardware Abstraction Layer application; the VMM Data Stream Scoreboard application; and the VMM Macro Library.
Chip development teams need to have confidence that their verification methodology is mature, full-featured and scalable.
The VMM Catalyst program allows EDA suppliers to leverage VMM technology and expertise to create tools, verification IP (VIP), training and services for chip development teams.
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