Product category:
Design and Development Software
News Release from: Synopsys | Subject: TMI methodology
Edited by the Electronicstalk Editorial
Team on 15 May 2008
Methodology eases 40nm modelling
At 40nm, the industry-standard BSIM-4 MOSFET model must now take into consideration mechanical stress effects in silicon and layout dependencies .
Synopsys has released the TSMC Modelling Interface (TMI) methodology, which has been developed from Synopsys' protocol for integrating custom device models into HSpice, HSIM and NanoSim transistor-level circuit simulators The TMI methodology delivers an innovative and efficient device modelling approach for TSMC's process technologies at 40nm and below
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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This new methodology, on average, improves simulation time and reduces memory usage by five times.
"To accurately model MOSFET transistors at 40nm and below, TSMC is exploring new modelling methodologies that deliver the best simulation performance without accuracy changes", said Min-Chie Jeng, Director of the Advanced Technology Modelling Division at TSMC.
"With the development of the TMI specification and computer software, TSMC overcomes the limitations of the sub-circuit macro modelling approach that has been in use for several generations of technology nodes".
"This leads to improvements in both 40nm computer simulation time and memory usage".
With device geometries shrinking at every new process node, MOSFET model complexity has increased in order to accurately represent the impact of new physical effects.
At 40nm, the industry-standard BSIM-4 MOSFET model must now take into consideration mechanical stress effects in silicon and layout dependencies that alter the characteristics of individual device instances based on their placement and proximity to other devices.
Standardisation of stress-effect modelling is extremely difficult because of the differences that exist in each application.
The process requires the customisation of models for every process.
"Our technology partnership with TSMC delivers an order-of-magnitude improvement in simulation time-to-results and is of tremendous benefit to our mutual customers using TSMC's 40nm technology node", said Paul Lo, Senior Vice President and General Manager of the Analogue/Mixed Signal Group at Synopsys.
"The success of this joint effort with TSMC has again demonstrated Synopsys' commitment to provide the most advanced device modeling and circuit simulation performance for the latest generation of silicon technology".
"In addition, the TMI methodology, based on Synopsys' protocols, establishes the foundation for TSMC's Spice Tool Qualification Program, which we anticipate will become an industry standard".
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