Software slashes design times

SystemC and SystemCrafter provided the Danish Technological Institute boosted the speed of re-use of test benches at different design stages and simulation by 10-100 times.

The Danish Technological Institute has successfully used SystemCrafter to demonstrate the benefits of a SystemC design flow.

SystemC and SystemCrafter were incorporated into a design flow from functional specification to implementation.

The DTI found that this approach resulted in fast protoyping and verification, re-use of test benches at different design stages and simulation 10-100 times faster than pure RTL.

Kim Bjerge, Senior Consultant at the Danish Technological Institute said, "Developing FPGA designs with SystemC and SystemCrafter SC means that with only a little extra learning, embedded software developers can design to hardware".

"They can then use the same language for both software and hardware development".

He added, "SystemCrafter SC gave us a quick and easy route from SystemC to hardware".

"Plus we could use our SystemC test bench to verify the gate level HDL, which was a significant time-saver".

SystemCrafter SC V3 was used in a number of examples to demonstrate the hardware/software codesign workflow, including a second order biquad type IIR filter used for coefficient calculation.

This has been implemented and tested on a Xilinx ML405 board with an embedded power PC.

The design flow started with a functional view written in C++, identifying the sub components and interfaces but with no implementation details.

The architecture view allocated each subcomponent to a hardware or software implementation.

The IIR filter was written in SystemC (system level) and then compiled to a gate level SystemC and corresponding HDL (VHDL) description using SystemCrafter SC V3.

It was then possible to simulate the system level and gate level descriptions using the same SystemC test bench.

The SystemC simulation times for 1000 samples were less than 1s at the functional level, 2s for system level and 23s for gate level.

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