Product category:
Design and Development Software
News Release from: TransEDA | Subject: PCI-X 2.0 verification suite
Edited by the Electronicstalk Editorial
Team on 22 August 2002
Verification suite checks up on new
PCI-X designs
The PCI-X 2.0 verification suite comprises the first commercial verification intellectual property (IP) for designs incorporating the newly released PCI-X 2.0 specification.
The PCI-X 2.0 verification suite comprises the first commercial verification intellectual property (IP) for designs incorporating the newly released PCI-X 2.0 specification The suite, part of TransEDA's Foundation Models system-level verification IP library, includes a comprehensive bus functional model (BFM), monitor, test suite, and property library to speed verification of designs incorporating the PCI-X 2.0 interface standard
This article was originally published on Electronicstalk on 30 Sep 2002 at 8.00am (UK)
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"We saw tremendous demand and an opportunity to be at the forefront of verification for what looks to be an important interface standard that can cut across application domains for years to come", said Tom Borgstrom, vice president of marketing at TransEDA.
David Dorrough, technical marketing manager at ServerWorks said, "Based on our previous success and experience using several of TransEDA's Foundation Models, we were eager to use their PCI-X 2.0 models too.
PCI-X 2.0 is an important part of our future product plans.
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PCI-X 2.0 offers enough bandwidth to support all foreseeable applications, plus it is backward compatible with the sockets that are already out there".
According to Borgstrom, "Many people buy third-party cores for interfaces like PCI-X and only get the register-transfer level (RTL) and testbenches for those cores.
That alone is not enough to completely verify their interface.
How their design drives that core and reacts with realistic system traffic is really the deciding factor in a successful implementation.
Our Foundation Models library provides the verification-specific interface and processor-side models that enable users to quickly build a system-level environment to verify their designs".
TransEDA's PCI-X verification suite includes full support for PCI, PCI-X 1.0, and PCI-X 2.0.
It provides an integrated and consistent way for engineers to verify the PCI/PCI-X interface of their designs under realistic and concurrent traffic conditions without having to spend months creating and debugging their own models.
The main components of the suite are as follows.
The bus functional model (BFM) is user-configurable, self-checking, and automated, with intelligent master and slave agents that drive and respond to transactions on the bus.
With greater ease-of-use than other commercial BFMs and support for multithreading and out-of-order split completions, the master and slave agents can be programmed, triggered and then ignored while a cycle is run.
The BFM can be easily installed into a users' testbench and can be statically or dynamically configured.
The monitor observes bus traffic and provides performance statistics so a user can see how efficiently their device moves data.
The monitor identifies bus protocol errors, logs all bus activity, and also provides transaction type versus response and control signal state coverage information so a user can determine which aspects of the bus protocol have been exercised during a simulation run.
The arbiter co-ordinates access to the bus by multiple agents in a system simulation.
Arbiter functions can be configured for different types of arbitration scenarios such as rotating or fixed priority, with or without lock agent priority.
The stimulus agent allows low-level sequences of vectors to be clocked onto the bus, response vectors to be captured, and captured data to be compared to a set of expected vectors.
Sets of regression tests and VN-Control test configuration files verify basic compliance.
The testbench and accompanying tests illustrate a wide range of parameters that a user can customise for specific designs.
The property library describes the PCI-X 2.0 specification in terms of expected and prohibited protocol behaviours.
Used with TransEDA's VN-Property DX dynamic property checker, it helps ensure that no PCI-X 2.0 operating rules were violated during simulation, and provides detailed protocol coverage metrics and reports.
Components of the library can also be used as building blocks to create higher-level properties.
TransEDA Foundation Models are compatible with leading hardware description language (HDL) simulators.
They include a transaction-level API for easy integration with existing verification environments or TransEDA's VN-Control application-specific test automation software, providing a complete system level verification environment.
VN-Control provides automatic test generation from a high level template and automatic results checking for target applications.
It can easily generate tests to verify that PCI-to-PCI-X bridges follow specific required producer-consumer ordering rules.
TransEDA's Foundation Models library offers robust, field-proven processor bus functional models, standard bus agents and monitors, and functional coverage models for use in existing HDL verification environments or with TransEDA's other products.
In addition to PCI-X 2.0, the library supports a number of other protocols, including PCI, PCI-X, HyperTransport, AMBA, and a number of processor families such as the Intel Pentium and Intel Itanium processor families and the Vr5464 MIPS processor from NEC.
The PCI-X 2.0 verification suite will be available in August 2002 and has a starting price of US $30,000 for a one-year subscription licence for the bus functional model and related simulation/testbench components; and US $15,000 for a one-year subscription license for the property library.
(This was Electronicstalk's Top Story on 22 August 2002).
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