Product category:
Electronics Manufacturing Materials and Consumables
News Release from: Tecan | Subject: Wafer-bumping stencils
Edited by the Electronicstalk Editorial
Team on 15 November 2001
Wafer-bumping stencils deposit paste
accurately
New-generation wafer-bumping stencils from Tecan Stencils Limited (TSL), are high-tolerance production aids which ensure optimum solder paste release characteristics.
New-generation wafer-bumping stencils from Tecan Stencils Limited (TSL), are high-tolerance production aids which ensure optimum solder paste release characteristics, resulting from mirror finish stencils with mirror finish aperture walls Wafer bumping stencils are used to accurately deposit solder paste directly onto silicon wafer die
This article was originally published on Electronicstalk on 12 Mar 2001 at 8.00am (UK)
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Electroformed wafer-bumping stencils
Electroformed wafer-bumping stencils from Tecan Stencils Limited (TSL) are used to accurately deposit solder paste directly onto silicon wafer die.
Wafer-bumping stencils maintain accuracy
Tecan is now producing stencils in the next-generation large format of 300 x 300mm, while maintaining close tolerance and high resolution across the whole image.
Following a reflow operation, the paste forms the conductive solder bumps required for I/O.
Highly accurate and repeatable quality are offered by the stencils, allowing users to cost-effectively reduce defects and rework while maximising the available yield from a given wafer - for optimum results.
Using specialised electroforming mandrels, the company produces highly accurate mirror finish stencils which also have apertures with exceptionally smooth side walls and a subtly narrower than normal trapezoidal cross-section.
This ensures optimum paste release characteristics - improving the consistency of solder paste volume and hence, ball size and regularity.
The stencils cater for the increasingly high component densities and pitches associated with components such as chip-scale packages (CSPs), micro ball-grid arrays (BGAs) and flip-chip designs.
For example, a typical stencil for a multi-die 6in wafer may require 300,000 apertures, or over 500,000 for an 8in wafer, with hole diameters of 60 to 125um.
The technology represents a significant step forward in the reduction of production costs for such increasingly miniaturised silicon substrate electronics components.
It also ensures compatibility with existing SMT processes.
Process control is a fundamental element in the success of CSP, BGA and similar packaging.
The adoption of Tecan electroformed stencils provides the ability to tightly control each assembly process to ensure repeatable high yields.
Designs can be submitted as CAD files and the company offers a maximum five-day despatch prototyping service.
The following CAD formats are accepted, Gerber (RS274X), GWK, DPF and HPGL.
All parts are produced within the company's strict ISO9002 quality-control regime.
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