Product category:
ATE Systems
News Release from: Teradyne | Subject: J973EP VLSI test system
Edited by the Electronicstalk Editorial
Team on 04 May 2001
Improved performance for VLSI and SoC
testing
The Teradyne J973EP VLSI test system made its first appearance in Europe at Semicon Europa.
The Teradyne J973EP VLSI test system made its first appearance in Europe at Semicon Europa The J973EP structural to full-performance test system includes technology breakthroughs such as quad-site testing of a system-on-chip (SoC) device and industry firsts for high-performance device manufacturers with demonstrations of new memory test, mixed-signal, and high-current voltage source options
This article was originally published on Electronicstalk on 15 Nov 2007 at 8.00am (UK)
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The expanded performance of the J973EP, with Real Time Enabling, provides high-performance device manufacturers with the flexibility to shift between structural and full-performance test, or balance both types of test, to minimise test cost.
The J973EP enables manufacturers of microprocessors, core logic, integrated processors and graphics devices with the ability to increase frequency, accuracy, timing edgesets, and pattern memory performance as required in order to minimize test cost.
The expanded performance of the J973EP with Real Time Enabling provides flexibility to shift between structural and full-performance test, or balance both types of test.
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Real Time Enabling on the J973EP empowers semiconductor manufacturers and foundries to cut costs by enabling test capability, in real time, to the performance level of their test system to the devices being tested.
Semiconductor manufacturers and subcontractors are able to maintain a test system platform capable of meeting long-term digital test needs, while meeting an occasional or temporary test need that results from testing a large variety of devices.
By using Real Time Enabling, customers reduce their fixed capital costs by matching tester capability to the level required by devices.
The J973EP's memory test option delivers the necessary fault coverage for today's complex new devices, high-speed embedded memory cells and specialty memory types, providing the characterization and debug tools you need to get your devices to market fast with the highest possible yields.
The J973EP's channel count flexibility and multiple power resources allows quad-site testing to dramatically improve throughput and reduce test cost.
The J973EP is fully compatible with the J973's VHF digitiser and time digitiser options and expands these capabilities with a suite of mixed-signal tools that greatly enhance throughput on production runs of high-speed VLSI devices.
The VHF digitiser option (VDO) provides the necessary capabilities for full characterization and single pass production testing of integrated graphics and core logic devices.
VDO delivers precise, flexible analogue sampling to ensure the highest accuracy and throughput for characterization and production test.
High-performance device designs are now based on the use of PLLs or DLLs (delay locked loops) to achieve high core speed and manage device timing skews.
PLL jitter test in production provides high performance device manufacturers the data needed to adjust design and/or process to minimise jitter and hence maximise device-operating speed.
The time digitiser option (TDO) provides 10ps typical RMS jitter measurement accuracy for analysing both short and long term jitter effects.
The ganged voltage source option, available up to 200A, provides characterisation of high-performance processors operating at high current levels.
The exceptional voltage accuracy of the GVS allows devices to run at higher operating speeds resulting in improved yields.
Located in the test head, near the device-under-test, the GVS responds to high current loads with superior dynamic performance.
Pause times can be reduced during the device power-up sequence, resulting in shorter test times and improving test economics.
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