Product category:
PCB Connectors
News Release from: Teradyne | Subject: Backplane connectors
Edited by the Electronicstalk Editorial
Team on 19 February 2003
Backplane technology for multigigabit
transmission
Copper backplane and connector technology is growing to meet multigigabit transmission needs, says Gautam Patel, Signal Integrity Engineer at Teradyne.
In today's interconnect marketplace, speed to market has become as important as system speed Until recently, connector companies could stay on the leading edge by producing the technology needed to enable equipment vendors to meet their hunger for bandwidth
This article was originally published on Electronicstalk on 6 Apr 2001 at 8.00am (UK)
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Datarate requirements for backplane connectors and systems began to increase in the 1990s and rose from 644Mbit/s to 2.5Gbit/s at the end of the century.
With technology currently capable of reaching up to 5Gbit/s, the backplane interconnect industry is now striving to meet the 10Gbit/s needs of its customers' next-generation platforms.
Copper backplane and connector technology is growing to meet multigigabit transmission needs with matched impedance systems incorporating advancements in plated through holes, laminates, devices and connectors that have already achieved datarates thought to be impossible two years ago.
The connector is still a key variable because it not only must be compatible to the electrical needs of a given chipset, but can also be a constraint to the packaging engineer in board layout and rack design.
Its size, footprint, pin density, routability and cost can easily outweigh its potential electrical benefit.
To meet the ongoing needs of high-speed backplane architectures, a high-speed interconnection platform, Teradyne's GbX connector, is available.
The connector has a modular design with the ability to integrate high-speed signals with power, guidance and other modules to optimise the connector for each card function.
In designing a high-speed system, a primary objective is impedance matching all the components in the signal path in order to minimise signal reflection.
When the digital bit stream approaches an impedance mismatch, a reflection occurs and is reflected back at the source at twice the transmission line length divided by the velocity of propagation.
This reflected energy continues to "bounce" between the source and mismatch until it is completely attenuated by material losses.
The various phases contained in these reflected waves tend to add or subtract components of the following bit streams, which translates into higher order frequency attenuation, inter-symbol interference and a degraded eye pattern.
The new interconnection platform has been optimised for 100ohm differential signals.
Multiple simulations were performed on the internal geometry of the connector to impedance match every segment of the signal path, including the mating interface to achieve 2.5% connector reflection at a rise time of approximately 50ps.
The launch reflections can easily dominate the connector reflections, depending on board thickness and a number of other parameters.
The twinaxial structure of the mating interface and the use of differential signalling provides low crosstalk at 50ps rise times.
The interconnection platform has less than 5% multiline crosstalk at 50ps rise times (raw at cable end).
At speeds at or exceeding 2.5Gbit/s, the plated through hole cannot be characterised as a simple capacitor.
The plated through hole signal launch in a PCB can be modeled as a series transmission line with a shunt element (or stub).
An undesirable effect is created when an upper layer trace is connected to another upper layer trace in the PCB-created resonant stub.
These resonant stubs need to be characterised as microwave structures because they are capable of degrading system performance.
As the thickness of the PCB increases, the stub gets significantly worse because of the increase in length.
The effort to stretch the bandwidth of the interconnect cannot compromise connection reliability.
As speeds surpass 2.5Gbit/s and line length requirements remain constant, the signal will experience significant attenuation as a result of the dielectric loss.
The attenuation in board materials can be shown in frequency domain.
Even a short distance of a high-loss board material can affect signal transmission.
If a system designer's goal is to push out the 3dB frequency (or 50% power point), 6.0in of FR-4 laminate (8mil line width, 0.08in board) reaches this point at approximately 3.0GHz.
Substituting a low-loss material moves the 3dB point beyond 5.0GHz.
While overall loss is dominated by dielectrics, conductor loss is also a contributor.
A simulation was performed to see the effects of varying trace width and length on eye closure at 3.125Gbit/s.
In the simulation, 9 and 12mil lines were used as well as 10.0 and 20.0in traces in Nelco 4000-13 laminate.
Also included in the simulation were two of Teradyne's VHDM-HSD (very high-density metric, high-speed differential) connectors on either end with 3.0in stubs.
The signal was driven with the Vitesse VSC 7226-01 serdes and the input voltage was 1.6V.
System designers are compensating for losses in high-speed backplane systems with semiconductor devices optimised to drive the signals across the backplane.
Common methods include, but are not limited to, CDR (clock and data recovery) devices, multilevel signalling adaptive equalisation and pre-emphasis.
Many of the new high-speed backplane devices are incorporating these technologies to achieve multigigabit datarates over the backplane.
Tradeoffs need to be considered before incorporating these compensation techniques.
In some cases, the pre-emphasis can have a negative impact on the signal performance if the trace length is short.
For short trace lengths, where the losses are minimal, the boosted high-frequency signals cause increased reflections, crosstalk and electromagnetic interference.
Pre-emphasis becomes not only application-specific but trace length-dependent.
A benefit to pre-emphasis is that it is relatively easy to implement in terms of circuit design and power consumption.
Backplane devices implementing CDR techniques introduce another set of challenges.
Because CDR circuitry is complex, there is an issue with DC real estate as well as increased power consumption.
For backplane applications, the signal density is high and therefore prevents the CDR technology from being implemented in a discreet manner.
More likely, the CDR device would have to be incorporated into an application-specific integrated circuit.
A benefit of using CDR is that the same circuitry works independent of trace length.
System architectures have also evolved to meet this need for speed through a significant move toward differential routing.
Differential routing provides dramatically increased performance at high speeds by running two identical trace signals close to each other with opposite signal polarity so that "noise," typically created at high signal speed, is canceed.
Backplane connectors, such as Teradyne's VHDM-HSD connector family, that are optimised to run differential signals, are very successful in meeting this need.
The latest models allow point-to-point system speeds up to 5Gbit/s.
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