Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: Texas Instruments (April 2001-March 2006)
Edited by the Electronicstalk Editorial
Team on 23 January 2003
Silicon Logic Engineering provides ASIC
design aid
Silicon Logic Engineering is to work with Texas Instruments to develop complex ASICs for customers in the wireless and wireline infrastructure, and high performance computing markets.
Silicon Logic Engineering is to work with Texas Instruments to develop complex ASICs for customers in the wireless and wireline infrastructure, and high performance computing markets Under the agreement, SLE will provide semiconductor design services and intellectual property (IP) to support the increasing demand for ASICs manufactured in TI's advanced 130nm and below process technologies
This article was originally published on Electronicstalk on 31 Mar 2006 at 8.00am (UK)
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TI's manufacturing processes, combined with SLE's optimised design techniques, offer customers an attractive cost reduction and integration roadmap for their ASIC designs.
The agreement with SLE also augments TI's ability to offer a turnkey "specification to production" engagement model that frees customers from resource-intensive ASIC implementation tasks.
"TI's collaborative approach to high-end ASIC design gives our customers access to the most experienced semiconductor design and manufacturing process expertise in the industry", said Steve Sutton, Vice President of TI's ASIC business unit.
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"The agreement with SLE provides an additional route to 130nm designs without tying up our customer's mission-critical resources for RTL implementation".
At the leading edge of semiconductor manufacturing, the linkage between process technology and design is increasingly critical, requiring much higher levels of collaboration and customer interaction than have been offered by traditional ASIC vendors.
Chip designers must also consider challenges that did not appear on designs implemented in older technologies.
For example, device packaging must be considered early on because of its effect on I/O performance and signal integrity.
Timing closure, test methodology and layout are also more closely affected by the manufacturing process and many OEMs are finding it easier to hand these concerns over to their ASIC supplier rather than dealing with them in-house.
"After reaffirming its intentions to continue being a major player in the ASIC market in November, 2002, this alliance with SLE adds further credence to the seriousness of TI's commitment", said Jerry Worchel, Senior Analyst for In-Stat/MDR.
With roots in the supercomputer industry, SLE has delivered more than 30 complex, right-first-time ASICs and system chips to a variety of networking and computing systems customers.
SLE also specialises in the development of semiconductor IP blocks that speed the completion and ensure the accuracy of complex ASIC designs.
SLE's SPI-4 Phase 2 (System Packet Interface Level 4 Phase 2) high-speed interconnection IP block, for example, is fully digital and uniquely optimised for high-speed designs.
Developed by the Optical Internetworking Forum (OIF), the SPI-4 Phase 2 standard is fast emerging as one of the most important integration standards in the history of telecommunications and data networking.
SLE's SPI-4 Phase 2 IP block will be ported to TI's 130nm SR40 manufacturing process for inclusion in customer's ASIC designs.
"SLE is very excited about the opportunity to collaborate with TI", said Jeff West, President of SLE.
"We are looking forward to working with TI's design and manufacturing teams to help our mutual customers get their big, fast ASICs to market quickly".
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