Product category:
Standard Logic Devices
News Release from: Texas Instruments (April 2001-March 2006) | Subject: CDCU877
Edited by the Electronicstalk Editorial
Team on 21 July 2003
PLL boosts memory module datarate
Texas Instruments has released the industry's first DDR-II phase locked loop for registered memory modules that supports datarates up to 800Mbyte/s.
Texas Instruments has released the industry's first DDR-II phase locked loop (PLL) for registered memory modules that supports datarates up to 800Mbyte/s Supporting the industry's highest frequency, the high-performance, low-skew, low-jitter, zero-delay buffer gives designers wider timing margins necessary in designing high speed DDR memory modules found in applications such as PCs, servers, workstations and communications
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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The CDCU877 DDR-II PLL is fully compliant with the JEDEC DDR-II standard and distributes a differential-clock input pair to 10 differential pairs of clock outputs and one differential pair feedback-clock output differential pair.
Combined with the SN74SSTU32864 DDR-II logic register, this device provides a total chipset solution and facilitates easier part sourcing for DDR-II memory modules.
The SN74SSTU32864 can be configured as a 25bit 1:1 pinout configuration or a 14bit 1:2 pinout, allowing users to work with a single part number for multiple DIMM configurations.
Output edge-control circuitry is used in the device to minimise switching noise in unterminated lines, improving signal integrity.
The device also supports the DDR-II low power, minimising switching noise into the SDRAM inputs on the DIMM, improving signal integrity and lowering system power consumption.
The CDCU877 is available today and comes in a 52-ball MicroStar Junior BGA and 40-pin MLF package.
Planned pricing for the CDCU877 is $3.50 per device in quantities of 1000.
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