Product category:
Standard Logic Devices
News Release from: Texas Instruments (April 2001-March 2006) | Subject: CDCE706
Edited by the Electronicstalk Editorial
Team on 24 October 2005
Clock multiplier puts three PLLs in one
A novel clock multiplier integrates three on-chip phase locked loop components to provide industry-leading flexibility and performance.
Texas Instruments has developed a clock multiplier that integrates three on-chip phase locked loop (PLL) components to provide industry-leading flexibility and performance, including cutting period jitter by up to 70% compared with existing solutions and minimising electromagnetic interference (EMI) Each of the device's six outputs can be programmed in-circuit or during operation for any clock frequency up to 300MHz
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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Developed in TI's radio frequency (RF) silicon-germanium process, the three PLLs of the CDCE706 can accept a crystal, LVCMOS or differential input and generate six clocks from a single clock source.
Using on-chip EEPROM technology, designers can easily program and save the device's register settings in nonvolatile memory so that no re-programming is required at power-up.
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Designers can also use the two-wire SMBus interface to dynamically reprogram the outputs as needed while the device is in the system.
The CDCE706 enables fast time-to-market by easing the design process while providing very low period jitter of less than 60ps.
The user only needs to define the input and output frequencies or the divider setting, which automatically sets the PLL parameters.
This in turn guarantees high loop stability and frees the user from manually setting the charge-pump current, filter components, phase margin or loop bandwidth.
TI's RF process technology allows integration of such features while maintaining excellent PLL frequency isolation.
In addition, the new device features very flexible output settings such as enable, disable, low-state, signal inversion, slew-rate control of 0.6 to 3.3ns, and variable output supply voltage of 2.3 to 3.6V.
Along with programmable spread spectrum clocking (SSC), these features provide designers a powerful tool to optimise their designs for the lowest electromagnetic interference (EMI).
Also, the device's high-resolution PLL dividers enable 0ppm output clock error for high frequency stability.
The CDCE706 is sampling today and will be in full production in Q1 2006.
Suggested resale pricing is $3.60 each in 1000-unit quantities.
A development kit and programming kit will be available to simplify PLL design and programming.
The CDCE706 will also be available in factory-programmed versions for high-volume applications.
The device is 3.3V supplied, operates in the industrial temperature range of -40 to +85C and is packed in a 20-pin thin shrink small outline package (TSSOP) package.
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