Optimised core jumps the queue to top benchmark

Tensilica has claimed the highest score ever reported on the Networking Version 2.0 benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC).

Tensilica - the only company to automate the design of optimised application-specific configurable processors for system-on-chip (SoC) design - has achieved the highest score ever reported on the Networking Version 2.0 benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC).

Tensilica's Xtensa LX processor is the first licensable processor core to complete certification on this challenging benchmark suite.

EEMBC benchmark scores, based on simulation, show that an optimised Xtensa LX processor core is significantly faster on a per-megahertz basis than the only two other processors certified to date, the 1GHz PowerPC 750GX and 1.4GHz PowerPC MPC7447A, both of which are full-chip, standard product processors.

The Xtensa LX processor delivers this outstanding performance while simultaneously delivering a 4x code density advantage and more than a 100x advantage in both die area and power dissipation.

Tensilica used two innovative features of its Xtensa LX processor architecture to achieve these outstanding results.

First, Tensilica made extensive use of custom FLIX (flexible length instruction extensions) instructions including seven different 64bit instruction word formats with up to eight parallel operation slots.

FLIX delivers VLIW-style parallel execution without the "code bloat" typically incurred by VLIW-style processors.

In fact, the dramatic 4x to 5x speedup achieved by the optimised Xtensa LX score versus the out of the box Xtensa LX score was accompanied by a reduction of total code size of nearly 2%.

Secondly, Tensilica selectively employed user-defined TIE (Tensilica Instruction Extension) queues to dramatically accelerate the IP packet check kernels.

TIE queues allows SoC designers to bypass the standard processor bus and directly import data into the execution units of an Xtensa LX processor, much in the same way that a dedicated hardware accelerator block would process data in an SoC design.

Whereas conventional processors are limited to a maximum data throughput of one 32 or 64bit data read or write every clock cycle, Xtensa processors with queues can sustain datarates of one transfer every clock cycle for every queue port, with a user-defined bandwidth of up to 1024bit per cycle.

Tensilica's Xtensa LX processor is the only processor that allows designers to bypass the conventional processor-bus-bottleneck in this way.

With Tensilica's patented technology, the queue interfaces and custom packet-header inspection instructions can be added to a processor within hours, complete with fully verified RTL and software tools and models.

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