Product category:
Intellectual Property Cores
News Release from: Tensilica | Subject: Xtensa V and Xtensa LX
Edited by the Electronicstalk Editorial
Team on 30 August 2005
SoC cores take advantage of latest 90nm
tools
Tensilica has enhanced its automated configurable processor design methodology to account for common integrated circuit design challenges with 90nm process technology.
Tensilica has enhanced its automated configurable processor design methodology to account for common integrated circuit design challenges with 90nm process technology These enhancements support the latest capabilities of the Cadence and Synopsys tools and include automated generation of physical design flow scripts that significantly lower power consumption, automate the input of user-defined power structures, and support crosstalk analysis
This article was originally published on Electronicstalk on 30 Mar 2005 at 8.00am (UK)
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"90 nanometre design presents significant new challenges for IC designers", stated Steve Roddy, Tensilica's Vice President of Marketing.
"By automating the script development for the best-in-class design tools, we can speed our customers' designs to market".
One of the big challenges of 90nm silicon is that dynamic power consumption rises dramatically.
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Tensilica counters this by automating the insertion of fine-grain clock gating throughout the Xtensa LX core and all designer-defined extensions.
Synopsys' Power Compiler is used for further power optimisations.
Another 90nm silicon challenge is the increased severity of IR drop across power rails.
New automatically generated Xtensa layout scripts automate the input of designer-defined power structure into the layout tools.
Interconnect parasitic effects are the third 90nm challenge.
Interconnects, which have dominated signal delay in all submicron technologies, are now critically affected by layout parasitic effects.
Therefore, interconnect modelling accuracy is a critical input.
New automatically generated Xtensa layout scripts also automate electrical parameter input from tool-specific technology files to better model parasitic effects.
Crosstalk avoidance and clock skew/insertion are critical design requirements for 90nm designs.
Tensilica's new scripts automatically support Cadence's CeltIC for crosstalk analysis.
Tensilica's new scripts enable "useful skew modes" in the Synopsys Astro and Cadence SOC Encounter place and route tools to deliver maximum achievable clock rates.
Tensilica has worked closely with Synopsys and Cadence to support their new generation of 90nm design tools.
Tensilica has automated the production of synthesis and implementation scripts for Xtensa processors.
These scripts are automatically generated for every Xtensa V and Xtensa LX processor configuration.
The Xtensa hierarchy is fully understood by these scripts and the scripts include full support for designer-defined TIE (Tensilica Instruction Extensions) language extensions to the base processors.
The automated scripts even support custom instructions that require more than one clock cycle to complete.
Logic dependencies are grouped automatically so the logic hierarchy is re-organised for timing optimisation.
Tensilica uses a bottoms-up approach with multiple passes on the top level to produce scripts that require no additional user modification.
Advanced SoC designers, however, are free to modify and extend these scripts to meet company-specific physical design rules or goals.
"Cadence Encounter tools have helped Tensilica to streamline the 90 nanometre design flow with the automatic generation of scripts", said Eric Filseth, Vice President of Product Marketing for Cadence Digital Implementation group.
"This will enable our mutual customers to achieve a fast, efficient path to silicon for their application optimised Xtensa-based designs".
"Tensilica understands and has worked with Synopsys to address the challenges poised by 90 nanometre technologies", said Lonn Fiance, Director of Strategic Alliances, Synopsys.
"Linking the 90 nanometre proven Synopsys Galaxy Design Platform with Tensilica's automatically generated synthesis and implementation scripts provide a faster path for Tensilica's customers to design customised processors in leading edge processes".
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