Configurable processor flies on ST 90nm process

STMicroelectronics has achieved first silicon success on a chip that proves Tensilica's Xtensa V configurable processor achieves a clock rate of 500MHz in a 90nm process technology.

STMicroelectronics has achieved first silicon success on a chip that proves Tensilica's Xtensa V configurable processor achieves a clock rate of 500MHz in a 90nm process technology.

ST's simulations on a second design expected to go into fabrication in a couple of months, using Tensilica's Xtensa LX processor, shows that Xtensa LX reaches 700MHz in 90nm technology, which makes it the industry's fastest synthesisable, configurable core.

ST configured the Xtensa V processor to typical networking multi-processor applications and optimised its implementation onto the target 90nm technology, with dedicated 32Kbyte cache design and advanced physical synthesis techniques.

The resulting silicon achieved 500MHz operations at 0.9V, while keeping a very low power profile of 0.16mW/MHz.

These results make the Xtensa LX and Xtensa V processors attractive, both for traditional CPU control applications, and for high-speed application acceleration like alternatives to hard-coded RTL (register-transfer-level) block designs.

Besides being fully programmable 32bit processors, the Xtensa configurable processors are much faster to design and are automatically verified and guaranteed correct by construction.

Designers can run their existing C/C++ algorithms through Tensilica's Xpres compiler to automatically customise the Xtensa LX processor in less than an hour, whereas a typical RTL design cycle usually requires six to nine months of design effort.

Tensilica worked closely with ST on this pilot project to evaluate the speed and ease of designing with Xtensa processors.

"We really appreciate the effort of ST to prove that the Xtensa LX processor is the fastest synthesisable, configurable core".

"Our mutual customers can be assured they will get the high performance they need in their designs by using ST's 90nm design platform", stated Chris Rowen, President and CEO of Tensilica.

"Those design teams that have the most demanding clock rate requirements should take a serious look at the ST high-performance 90nm process".

ST's 90nm design platform is intended for system-on-chip (SoC) and ASIC solutions that target wireless, consumer and networking applications.

It features as many as nine metal layers of copper interconnect, low-k dielectric, dual-gate oxide, and dual-Vt transistors.

Standard cell libraries containing more than 1000 cells feature 11ps gate delay and a library density of more than 400,000 gates per square millimetre.

"Many of our ASIC customers are looking at Tensilica's Xtensa processors as a way to add extra flexibility to their designs, especially as they make the investment in 90nm technology", stated Flavio Benetti, WLI Division ASIC BU Director, STMicroelectronics.

"The high clock rates possible with these processors make them an attractive alternative to RTL design, particularly because they can be modified to match the particular application so quickly".

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