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News Release from: Tensilica | Subject: Xtensa 6
Edited by the Electronicstalk Editorial
Team on 25 October 2005
Processor promises faster SoC design
Tensilica has announced a new version of its Xtensa processor family - the Xtensa 6 configurable and extensible processor core for system-on-chip (SoC) design.
Tensilica has announced a new version of its Xtensa processor family - the Xtensa 6 configurable and extensible processor core for system-on-chip (SoC) design As a replacement for Tensilica's workhorse Xtensa V processor, Xtensa 6 adds three major enhancements: the ability to automatically customise it from a C/C++ based algorithm using Tensilica's proven Xpres compiler; approximately 30% lower power than Xtensa V; and advanced security provisions in MMU-enabled configurations through a "no execute" bit that provides enhanced protection against malicious code
This article was originally published on Electronicstalk on 30 Mar 2005 at 8.00am (UK)
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"Xtensa 6 provides SoC designers with the fastest, most cost-effective SoC block design tool in the industry", stated Steve Roddy, Vice President of Marketing, Tensilica.
"By using our popular Xpres compiler, in less than an hour designers can create application-specific building blocks that can serve as either conventional control processors or as a suitable alternative to RTL-based hardware block design, but in a fraction of the time and without the verification headaches".
"We expect this product to significantly widen our customer base because it fully automates time-and-resource intensive IC design steps and adds programmability to the post-silicon design, a crucial value-add enabler in fast-moving, high-volume SoC markets".
Further reading
Optimised core jumps the queue to top benchmark
Tensilica has claimed the highest score ever reported on the Networking Version 2.0 benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC).
Core claims top performance at 90nm node
The Xtensa LX reaches the highest clock rate published to date of any licensable 32bit processor in 90nm technology.
SoC cores take advantage of latest 90nm tools
Tensilica has enhanced its automated configurable processor design methodology to account for common integrated circuit design challenges with 90nm process technology.
Tensilica's Xpres compiler enables the rapid development of optimised SoC building blocks without requiring designers to hand code their hardware using design languages like VHDL and Verilog, which take months of design and verification effort.
Instead, designers input the original algorithm that they're trying to optimise, written in standard ANSI C/C++, and the Xpres compiler, coupled with Tensilica's automated processor generation technology, automatically generates an RTL (register transfer level) hardware description and associated tool chain.
The Xpres compiler automatically determines which functions should be accelerated in hardware and generates a comprehensive hardware/software solution for those functions.
No RTL coding is required; the Xpres compiler automatically generates the necessary RTL code that is preverified to be correct by construction.
In less than an hour, the resulting hardware block is delivered electronically in the form or a preverified Xtensa 6 processor core that has been optimised for that exact application.
The correct by construction generated RTL removes the verification headaches associated with hand-generated, nonprogrammable hardware blocks.
The Xpres compiler allows designers to quickly evaluate different configurations and make area/speed/power tradeoffs.
It also preserves C code portability, generating Xtensa 6 processors that can be re-used over a range of similar application software code.
Similar code can take advantage of the acceleration without any modification due to the automatically generated C/C++ compiler associated with that particular configuration.
Additionally, the Xpres compiler also works with Tensilica's flagship Xtensa LX processor, meaning that Xpres compiler users can rapidly explore a wide range of hardware alternatives.
Tensilica significantly improved the base architecture of the Xtensa 6 processor, resulting in a 25-30% improvement in power dissipation.
Several techniques were employed.
Tensilica used both fine-grain clock gating, which turns off power to small sections of the processor when not in demand, and coarse-grain clock gating, which conserves power throughout much larger portions of the chip.
For example, when a processor activity such as a cache-line fill occurs, coarse-grain clock gating is activated, saving valuable power.
In this newest member of the Xtensa processor family, Tensilica employs advanced security provisions in the Xtensa MMU (memory management unit) configuration option similar to those AMD and Intel have provided for personal computers.
Whereas AMD calls the feature enhanced virus protection (EVP) and Intel calls it execute disable (XD), it is generically known as NX - for no execute.
NX provides the ability to protect portions of memory so processor instructions can't execute in those areas.
In Xtensa 6 configurations that employ the full virtual memory capability of the Xtensa MMU, the new security features of the Xtensa 6 design set some areas of memory off bounds, thus helping to prevent worms and other types of malicious code from executing functions.
This feature will be of interest to designers planning to run the embedded Linux operating system on Xtensa 6 processors, as this feature will be incorporated in future versions of the Linux operating system.
Tensilica's new Xtensa 6 processor is available now.
Licensing fees for a single processor configuration with perpetual usage rights start at $350,000.
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