Product category:
Design and Development Software
News Release from: Tensilica | Subject: Xenergy
Edited by the Electronicstalk Editorial
Team on 27 February 2007
Software takes holistic view of SoC
power drain
Energy estimator helps SoC designers cut processor and local memory energy requirements by up to half by making intelligent design tradeoffs.
To address the growing need to reduce power consumption in embedded systems, Tensilica has released the Xenergy estimator, a unique energy estimator for both Xtensa configurable processor and Diamond Standard processor users By using the Xenergy tool to optimise for energy early in the SoC design cycle, designers can cut processor and local memory energy requirements by up to half by making intelligent design tradeoffs
This article was originally published on Electronicstalk on 1 Apr 2008 at 8.00am (UK)
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"Xenergy will naturally appeal to designers of portable, battery-driven devices such as cellular phones and personal media players, but also to designers of complex SoCs in home entertainment and networking devices where heat is becoming a huge issue", stated Chris Rowen, Tensilica's President and CEO.
"Tensilica is the first company to provide a realistic way to easily estimate the overall energy impact of different processor configurations and extensions together with application code tuning on each processor with its memory subsystem".
"The improvement in power at the architectural level is quite dramatic and productive, often dwarfing the power savings painfully achieved at the RTL and physical design levels".
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Total energy to complete a task (power dissipated over time taken for the task to complete) can be dramatically reduced by customising a Tensilica Xtensa processor.
Sample results show that with identical process technology, the energy improvement from processor customisation can range from 2x to 83x.
The new Xenergy energy estimator works by computing a power-consumption estimation per-cycle for each different instruction of an Xtensa configurable processor or Diamond Standard processor.
For each user-defined instruction extension in an Xtensa processor, created using Tensilica's powerful TIE (Tensilica Instruction Extension) language, Xenergy creates an energy estimate for the newly created instruction, including modelling the energy consumed by all locally attached memories that are active for a given instruction.
Then, using the instruction profile created by Tensilica's pipeline accurate instruction set simulator, a detailed energy consumption profile is created for the user's specific application code.
The Xenergy tool is used during the process of configuring an Xtensa processor.
Designers can immediately see the effect on total energy consumption when they add configuration options (multipliers, DSP engines, a floating point unit, and many additional configuration choices) and designer-defined instructions.
They can see the effect of different interface options as well as memory subsystem options.
A focus on total energy consumption is key.
Too often, designers will focus on a static milliwatts per megahertz power figure, but ignore the total energy consumption of the workload.
For example, a designer may add a set of custom instructions to a processor that increase the total size of a processor core, which increases the average power per clock cycle (increasing the milliwatts per megahertz).
But if that custom instruction set addition dramatically lowers the total clock cycles required to perform a given functional workload (a target C code application) then the total energy consumed (power-per-cycle multiplied by total cycle time) can be reduced.
Example: an increase in power per clock of 20% is offset by a 3x speed up in instruction execution.
The milliwatts per megahertz power consumption increases 20%, but total energy consumption is actually reduced by 60%.
The reduction in required execution cycles allows the system either to spend much more time in a low-power sleep state, or to reduce frequency and voltage, leading to a sharp reduction in both dynamic and leakage power.
The inclusion of memory power consumption is another key aspect to the new Xenergy tool.
Imagine a scenario where designer-defined processor extensions are used to create custom state registers and register files within an Xtensa processor core, not to appreciably improve execution performance, but instead aim at significantly decreasing accesses to local memory, thus decreasing overall energy.
The Xenergy program points out this energy decrease, making it easy for the designer to weigh area, performance and power tradeoffs early in the processor configuration process.
The Xenergy energy estimator is also useful for optimising software, even on completed chips where the processor - whether it is an Xtensa configurable processor or a Diamond Standard core - cannot be changed.
Traditionally, software developers tune their code for performance or code size using Tensilica's standard profiling tools.
Now they can use the Xenergy tool to fine tune their C code to reduce energy dissipation by the processor and its memories.
For example, a developer might use the feedback provided by the Xenergy tool to decide to restructure the allocation of data structures in local and main memories to reduce memory and bus accesses, which will lower overall energy expenditures.
Tensilica's Xenergy tool is available now as part of a Tensilica Software Development Kit licence, which includes all software development tools, the instruction set simulator, and the Xtensa Xplorer design environment.
For users of the Diamond Standard series of processors, pricing for the software development kit starts at US $1000 per seat per year for a node locked licence.
For Xtensa processor users, pricing for a software development kit starts at $2000 per seat per year for a floating node tool seat.
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