Processor cores upgrade to new standards

Second-generation processor cores include additional multiplier and divider units, hardware optimisations to lower memory power, and an optional bridge to AXI-based Amba systems.

Tensilica has enhanced its successful Diamond Standard processor product line.

The new second-generation Diamond Standard processors include several new features including additional multiplier and divider functional units, several hardware optimisations that lower memory power by up to 30%, and an optional bridge to AXI-based Amba systems.

"In their first year, the Diamond Standard cores have far exceeded our expectations", says Chris Rowen, Tensilica's President and CEO.

"Our customers have told us they were looking for the high performance, low power and small size of the Diamond Standard processor family".

"So we decided to make the family even faster, even lower power and even smaller".

"The second generation of Diamond Standard processor cores demonstrate our commitment to continued leadership in processor cores across the full range of control, DSP and media applications".

The Diamond Standard processor product line includes five controller/CPUs and two digital signal processors (DSPs) that are being introduced or updated.

The controllers include: the Diamond 106Micro the smallest licensable 32bit ultra-low-power cacheless RISC controller; the Diamond 108Mini Rev B an ultra-low-power cacheless RISC controller with tightly coupled local memories, a hardware multiplier and divider, rich interrupt architecture and minimal gate count for low silicon cost; the Diamond 212GP Rev B a flexible mid-range RISC controller with DSP instructions, instruction/data caches, and tightly coupled local memories; the Diamond 232L Rev B a flexible mid-range applications processor with DSP instructions and a memory management unit (MMU) for Linux OS support; and the Diamond 570T Rev B a high-performance three-issue static superscalar applications processor with over twice the performance per megahertz of an ARM11 (based on EEMBC benchmarks).

The two DSPs in the updated Diamond Standard Processor family are: the Diamond 330HiFi Rev B a low-power 24bit audio processor for all popular audio and speech codecs, based on the market-leading Xtensa HiFi 2 audio engine; and the Diamond 545CK Rev B billed as the highest performance licensable DSP on the market (based on BDTI Benchmarks) with a three-issue VLIW (very long instruction word) processor.

The second generation Diamond Standard processors include three significant enhancements.

First, the arithmetic capabilities of the controllers have been significantly enhanced, reducing the need for external DSPs.

An integer divider has been added to the Diamond controllers (Diamond108Mini, Diamond 212GP, Diamond 232L and Diamond 570T).

This hardware divider significantly improves the performance of these processors on complex arithmetic applications like GPS, automotive applications, motor control, and engine control.

A 32x32 single-cycle, pipelined multiplier has been added to the Diamond 108Mini, Diamond 212GP, and Diamond 232L processors, thereby improving the performance of these processors on common DSP algorithms (the Diamond 570T already had a multiplier).

Secondly, edge-triggered interrupts have been added to all Diamond Standard processors, easing system design and giving faster interrupt response than level-triggered interrupts.

Now, all Diamond Standard processors are available with up to 22 interrupts and six priority levels.

Thirdly, Tensilica has added support for relocatable exception vectors, which enables customers to change the memory location of exception handlers in software post-silicon.

This gives more flexibility to the designer and eases system design.

Tensilica has made several changes that allow power on the memory interfaces to be reduced by up to 30%.

One of the biggest changes included memory system optimisations that leave local data memories turned off for longer periods of time without negatively impacting performance.

Also, Tensilica has designed in additional power-down modes, including external power-down of the trace port control and on-chip debug modules, lowering overall system power.

"Low power is sometimes the biggest concern for SOC designers as they evaluate processor cores", adds Rowen.

"We are committed to continue to offer the industry's best mix of low power and high performance in our cores".

Tensilica now offers an optional Amba AXI bridge in addition to the Amba AHB-lite that has been available to Diamond Standard processor customers.

These AHB and AXI bridges enable designers to easily integrate Diamond Standard cores into Amba-based SoCs.

All Tensilica Diamond Series controller and DSP cores are available with the native high-performance Tensilica PIF processor interface that is suitable for bridging to any on-chip bus (eg OCP, CoreConnect), or with an Amba AXI or AHB-Lite interface.

SoC designers therefore can choose any common on-chip bus and leverage existing infrastructure and peripheral component sets.

The second generation of the Diamond Standard processors is available now.

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