Product category:
Intellectual Property Cores
News Release from: Tensilica | Subject: Xtensa 7 and Xtensa LX2
Edited by the Electronicstalk Editorial
Team on 14 December 2007
Processor cores put more into SoC
designs
Configurable processor families gain new hardware options and software tool enhancements to appeal to an even wider audience of SoC designers.
Tensilica has upgraded its two Xtensa configurable processor families (the Xtensa 7 and Xtensa LX2) with new hardware options and software tool enhancements that make it appeal to an even wider audience of SoC designers Highlights of these capabilities include a new, smaller general purpose register file option, new integer multiplier and divider execution unit options, two new Amba 3.0 bridge options, as well as an easy-to-use new configuration tool that analyses source C/C++ code and automatically suggests VLIW (very long instruction word) instruction extensions that lead to 30-60% improvements in general purpose code performance
This article was originally published on Electronicstalk on 30 Mar 2005 at 8.00am (UK)
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These new capabilities provide designers with the most productive configurable processor design environment, with automated features that ensure each processor design is correct by construction.
"This new product generation represents a significant enhancement of our Xtensa processor line in three dimensions - in support of even leaner deeply embedded 'data engine' configurations, in richer high-end system support, and in significantly enhancing our processor analysis, modelling, and software tools", explains Chris Rowen, Tensilica's President and CEO.
"Our Xtensa processors are already widely demanded".
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"These advances both help existing Xtensa users design more sophisticated SoCs and enable new designers to get the full benefits of configurable processors with less design effort and design time than ever before".
Steve Roddy, Tensilica's Vice President of Marketing, adds: "The Xtensa configurable processor architecture is so flexible that it is currently in production in functions as varied as a simple cacheless controller, a mid-range Linux applications processor, a high-performance three-issue VLIW general purpose processor, an audio DSP, a video DSP engine, high performance image processors, and high performance network processors".
"No other processor architecture comes close to matching this versatility".
The five most significant new hardware options introduced by Tensilica include: a 16-entry register file, a relocatable exception vector option, a low-area multiplier, an integer divider, and new AMBA-compatible bridges.
First, Tensilica has added support for a smaller 16-entry main register file in the Xtensa processor, in addition to the existing support for 32-entry and 64-entry configuration options.
This enables the instantiation of a very small processor core that competes in area and power with 8 and 16bit microcontrollers and yet provides the performance, flexibility, and features of a 32bit controller.
Secondly, by adding support for relocatable exception vectors, Tensilica is enabling customers to change the memory location of exception and interrupt handlers in software post-silicon.
This gives more flexibility to the SoC designer and eases system design.
Thirdly, Tensilica has added a low-area multicycle 32x32 multiplier configuration option, which enables the design of an Xtensa configuration that is very small in area, but still has good performance on multiply-rich applications, such as MP3 decoding.
This gives designers a new choice that is more area efficient than the existing single-cycle fully pipelined 32 and 16bit multiplier configuration choices and still much higher performance than pure software emulation of multiply instructions.
Fourthly, Tensilica has added a low-area divider configuration option, requiring only about 4000 gates.
This provides a standardised and powerful way to boost performance on numerically intensive applications such as those running on GPS (global positioning satellite) controllers and real-time control code applications that are typical of servo, motor and engine control.
Finally, Tensilica has added the Amba 3 AXI bridge as a click-box configuration option.
This, in addition to the existing Amba 2 AHB-lite (Advanced High-performance Bus-lite) bridge option, allows designers to seamlessly drop Xtensa processors into Amba-based systems and eases the use of Xtensa processors with other Amba peripherals.
Tensilica has made many significant enhancements to its software development toolkit and the Eclipse-based Xtensa Xplorer design environment to make it even easier and faster for designers who have never used configurable processors before.
The most important of the processor configuration tool enhancements is the automated Flexible Length Instruction Extension (FLIX) generator for Xtensa LX2, which profiles a designer's target C code and suggests VLIW instruction specifications that can significantly accelerate the most critical code.
By allowing two or three instructions to execute simultaneously, FLIX allows an Xtensa LX2 processor to act as a two- or three-issue VLIW CPU.
Designers can accelerate general purpose code between 40-60% by using simple, general purpose VLIW instructions.
This tool eliminates the need for the designer to analyse the code for areas that can be sped up in this way, significantly speeding the design experience.
After the processor core has been created using these new VLIW instructions, software developers programming the Xtensa core need only use the standard Xtensa C/C++ Compiler (XCC), which automatically extracts the instruction-level parallelism from C/C++ code and bundles operations into VLIW instructions whenever possible.
So, the programmer does not have to modify the application C/C++ code to take advantage of the VLIW instruction extensions to speed up the code.
Secondly, Tensilica has introduced the "Manual Fusion Editor", a graphical tool that enables the SoC designer to quickly and graphically create chains or fusions of fundamental computation operations in order to improve performance.
For example, basic add and shift operations can be combined to form an add_shift instruction that executes in one cycle.
This add_shift instruction could replace two sequentially issued instructions (add followed by shift), thus saving a clock cycle and saving code size.
As with the FLIX Generator, the operation fusion instructions created by the Manual Fusion Editor are included in the finished processor core RTL and implemented by the SoC designer into silicon.
Software developers take advantage of these new instructions merely by using the standard Tensilica software development environment.
Fused instructions are automatically inferred by the Xtensa C/C++ compiler (XCC), so that the application C/C++ code does not need to be modified.
Thirdly, designers will experience an average of 20% compilation run-time speed improvement for C/C++ source files in the XCC compiler, the centrepiece of the Xtensa compiler tool chain.
This optimising compiler allows designers to run their C and C++ code on Xtensa processors, taking full advantage of all optimisations made to that processor.
To increase code execution speed and reduce code size, XCC employs sophisticated multilevel optimisations such as function inlining, software pipelining, static single assignment (SSA) optimisations, and other code generation techniques.
Tensilica's enhancements make XCC not just one of the fastest compilers for 32bit processors, but also the most efficient, with exceptional code density.
Fourthly, Tensilica offers a new dynamic loader, a software tool that allows binaries to be loaded in different memory addresses at run time.
This is useful, for example, for audio and video codecs, so that the same codec can be loaded into different memory locations at run-time depending on available memory.
With the fifth major enhancement, Tensilica has sped up the execution of its cycle-accurate instruction set simulator (ISS) by 15 to 30%.
Likewise, the TurboXim fast functional simulator, which already executes at 50x the speed of the ISS, has also received numerous enhancements that improve its execution speed.
Finally, this release of the Xtensa software tools also enhances the functionality of the Xenergy energy estimation tool by adding visualisation and automatic cache energy search tools to the Xplorer Eclipse-based IDE.
Xenergy generates an energy profile of the Xtensa processor and its memory subsystems for application code by modelling each instruction and its memory accesses while the application is being executed.
The additions in this release include not only the ability to visually view and compare the energy profiles, but also a tool that automatically sweeps over different instruction and data cache configurations and graphically charts the energy profile for the application code on the particular Xtensa configuration for each cache configuration.
Xenergy is a valuable tool in the system designer's toolkit to guide in the energy-efficient choices to make while configuring an Xtensa processor, writing application-specific "tie" instructions, and deciding the write memory and cache configuration.
All of these enhancements have started shipping with the November 2007 release of Xtensa LX2 and Xtensa 7 processor cores and the Tensilica software development tools.
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