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News Release from: Tensilica | Subject: Xtensa LX2 configurable processor
Edited by the Electronicstalk Editorial
Team on 29 February 2008
System improves multiprocessor
flexibility
Using Tensilica allowed the Smart Memory team to focus on creating a flexible memory system that supports many different memory models
Stanford University's Smart Memories Project has used Tensilica's Xtensa LX2 configurable processor to develop a multiprocessor computing infrastructure for next-generation applications The Stanford Smart Memories Project has developed a prototype system on chip (SOC) design that provides the user with the ability to program both the processor and the memory system of a chip-level multiprocessor
This article was originally published on Electronicstalk on 30 Mar 2005 at 8.00am (UK)
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Top score posted for licensable processor core
Tensilica has announced that it has posted the highest score ever recorded for a licensable processor core, and the highest absolute score ever published for any processor on EEMBC.
Configurable processors enable latest DSL design
UpZide is to develop a reference design using multiple Xtensa LX processors from Tensilica to implement the VDSL2 standard.
Using Tensilica allowed the Smart Memory team to focus on creating a flexible memory system that supports many different memory models, including message passing, coherent shared memory and transactional memory.
The design is being evaluated for possible commercial deployment by a couple of large semiconductor companies.
"It's exciting to see our processor cores enabling ground-breaking research on next-generation computing architectures", said Chris Rowen, Tensilica's President and CEO.
Further reading
Optimised core jumps the queue to top benchmark
Tensilica has claimed the highest score ever reported on the Networking Version 2.0 benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC).
Core claims top performance at 90nm node
The Xtensa LX reaches the highest clock rate published to date of any licensable 32bit processor in 90nm technology.
"Universities play a key role in driving major electronics innovations, especially in the grand-challenge problems in scalable multiprocessor architectures and software paradigms".
The Stanford team configured Xtensa as three-way issue VLIW processors with a seven-stage pipeline, 64 general purpose registers and a 32bit floating point using the TIE (Tensilica Instruction Extension) Language.
The Smart Memories group has defined new interfaces to the memory, which allows the processor to respond to the meta-data bits in the memory so it can support various kinds of cache coherence.
The resulting system is a hierarchical multiprocessor.
Two Tensilica processors are placed in a tile, along with a number of programmable memory mats.
Four tiles are then grouped with a programmable local memory controller to form a quad and quads interconnect with each other and memory controllers through an on-chip network to form a Smart Memory chip.
Stanford researchers designed Smart Memories to efficiently support different programming models, allowing an application to be programmed and run in the model that gives the best performance and/or programming ease.
Smart Memories can reconfigure its memory system to provide the memory access requirements for each of three major models.
The Shared Memory/Multithread programming model gives the programmer a cache coherent shared memory environment.
The Streaming programming model is especially useful in high-performance data-parallel applications, such a multimedia and DSP.
The Transaction programming model offers a simpler way to parallelise applications than using different threads.
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