Product category:
Design and Development Software
News Release from: Tensilica | Subject: Xenergy
Edited by the Electronicstalk Editorial
Team on 01 April 2008
SoC design tool predicts power
consumption
Hardware designers can drive Xtensa processor configuration choices to dramatically lower the total clock processor cycles required to perform a given functional workload.
Tensilica has added a new graphical user interface (GUI) to its popular Xenergy estimator, a unique energy estimator for both Xtensa configurable processors and Diamond Standard processors This "first of its kind" tool allows software developers to evaluate tradeoffs, so their software can be optimised for power, and lets hardware designers optimise the design of Xtensa configurable processors for total energy consumption
This article was originally published on Electronicstalk on 27 Feb 2007 at 8.00am (UK)
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"Today, total energy consumption is a primary design consideration for both hardware designers and software developers in most market segments", says Steve Roddy, Tensilica's Vice President of Marketing and Business Development.
"Often, it isn't intuitive which design decisions will have the biggest impact on overall energy consumption for a new SoC design".
"By using Xenergy, designers can quickly evaluate the tradeoffs and know that they've picked the most energy efficient way to design new products".
Further reading
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Configurable processor technology has long been known for its potential to accelerate performance.
But tailoring a processor to a given task can also be used with energy minimisation as a key consideration.
Using Xenergy, hardware designers can drive Xtensa processor configuration choices to dramatically lower the total clock processor cycles required to perform a given functional workload, thereby reducing total energy consumed.
Designers pick from a menu of different configuration options and add custom processor extensions to try to reduce total core power consumption.
The Xenergy energy estimator calculates total energy consumption for a specific software workload on a candidate processor configuration.
Comparisons between candidate processors are graphically displayed.
Output can be a simple text file or a colourful graph for easy evaluation.
Tests of processor configurations for common embedded processing kernels such as dot product, the Advanced Encryption Standard (AES) encryption, Viterbi decoding, and fast Fourier transform (FFT) show that the energy improvements from processor customisation can range from 2x to 83x (all comparisons using common process, design flow and libraries).
The Xenergy estimator can also be used to evaluate the power savings potential of different process technologies, instruction and data cache sizes, RAM and ROM sizes, and many other Xtensa processor configuration options.
Even after a processor configuration is chosen, or after an SoC has been fabricated, software developers can also use the Xenergy estimator to fine tune their C code to reduce energy dissipation by the processor and its memories.
For example, a developer might use the feedback provided by the Xenergy tool to decide to restructure the allocation of data structures in local and main memories to reduce memory and bus accesses, which will lower overall energy expenditures.
The Xenergy estimator gives the software developer fast, visual feedback and pinpoints the code hot spots that are consuming the most processor cycles and generating the most memory accesses.
Xenergy, with its new graphical user interface, is shipping now as part of Tensilica's Software Development Kit, which includes all software development tools, the instruction set simulator, and the Xtensa Xplorer design environment.
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