PVS rule files now for 180nm technology

Synopsys' Hercules Physical Verification Suite (PVS) rule files are now available for Tower Semiconductor's release of 180nm high-voltage technology.

Synopsys and Tower Semiconductor have jointly announced that Synopsys' Hercules Physical Verification Suite (PVS) rule files are now available for Tower Semiconductor's release of 180nm high-voltage technology.

The availability of Hercules rule files for both design rule checking (DRC) and layout versus schematic (LVS) on this specialised process is the result of close cooperation between the two companies.

Hercules rule files are also supported in Tower's standard logic technology processes.

"Tower's continued support of Hercules PVS for sign-off verification enables our customers to continue working in the Synopsys design environment for our specialised technology offering," said Yaakov Milstain, vice president and general manager for design services at Tower.

"This joint endeavor is evidence of our strong relationship with Synopsys, one of the leading EDA providers".

The Hercules DRC rule file development, including support for specialised 180nm high-voltage devices, has been qualified for sign-off using a rigorous set of specialised test cases.

Hercules LVS can also be used with Synopsys' Star-RCXT extraction solution to merge highly accurate parasitic data with the schematic-level devices.

This unique capability delivers greater simulation accuracy while allowing circuit designers to design and analyse circuits at a familiar level of detail.

"The availability of Hercules PVS rule files for Tower's high-voltage technology demonstrates the broadening foundry support for Hercules PVS on specialised processes," said Anantha Sethuraman, vice president of marketing, Design for Manufacturing, at Synopsys.

"Qualification by foundries such as Tower Semiconductor enables our mutual customers to benefit from higher DRC performance and a proven transistor flow".

With its design for manufacturing (DFM) tools, Synopsys is expanding on what is already the industry's most comprehensive DFM solution that spans from RTL to silicon.

Synopsys' DFM product family addresses critical manufacturability and yield issues with the following products: IC Compiler physical design solution, PrimeYield LCC, PrimeYield CMP and PrimeYield CAA, Hercules PVS, Proteus OPC, CATS mask data preparation product, SiVL lithography verification tool, patented PSM technology, and physics-based TCAD suite of simulation products.

Synopsys' Manufacturing Yield Management (MYM) solutions extend directly into the fab, providing customers real time access to yield data and the analysis capability needed to reduce random, systematic and parametric defects.

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