CMOS process produces rad-hard SoC

Prototype radiation-hardened SoC controller for space applications is fabricated on Tower's Fab2 0.18um process technology.

Tower Semiconductor has successfully manufactured a prototype radiation-hardened SoC controller for space applications.

The SoC is being fabricated for fabless company Ramon Chips on Tower's Fab2 0.18um process technology.

The SoC controller operates at 150MHz, and the on-chip SpaceWire interface achieves 250Mbit/s transfer rates.

The product is expected to sustain cosmic radiation and harsh environmental conditions and is thus useful for all space missions in earth-orbiting satellites.

It is also intended for high-reliability avionic applications.

The SoC controller has been designed and fabricated using Ramon Chips' proprietary RadSafe methodology and standard cell library, which assure radiation hardness of parts fabricated in Tower Semiconductor's manufacturing lines.

Another prototype chip fabricated using the same RadSafe library and the same Tower Semiconductor 0.18um CMOS process has been tested successfully at radiation levels of 300krads and had sustained no radiation-induced latchups and less than 10e-13 soft error events per bit per day at LET levels exceeding 100MeVcm2/mg.

"We are satisfied with the accomplishment of the radiation hardened high performance product on Tower's 0.18um technology platform", says Prof.

Ran Ginosar, CEO of Ramon Chips .

"Tower's team assisted greatly in upgrading the standard cell library to make it radiation hardened".

"We see several promising business opportunities based on this technology accomplishment".

"We are happy that Ramon Chips product demonstrated the resilience and versatility of Tower's process technology", says Dani Ashkenazi, CMOS Product Line Manager at Tower.

"The proven rad hard libraries add another dimension to Tower's offering and may serve penetrating additional customer domains".

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