Product category:
Design and Development Software
News Release from: Teklatech | Subject: FloorDirector
Edited by the Electronicstalk Editorial
Team on 17 March 2008
Floorplanning tool aids SoC integrity
Advanced floorplanning software tool offers SoC power-shaping, clock-cycle stretching and robustness to on-chip-variation.
Teklatech has announced the immediate availability of its new FloorDirector product - an advanced floorplanning software tool FloorDirector offers SoC power-shaping, clock-cycle stretching and robustness to on-chip-variation, accelerating the broad adoption of advanced nanometre geometries
This article was originally published on Electronicstalk on 28 May 2008 at 8.00am (UK)
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FloorDirector reduces dynamic IR drop and supply noise by intelligent power shaping, flattening power peaks, thus improving signal and power integrity.
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The tool enables semiconductor design teams to address dynamic power issues, optimising their SoCs for low power and minimising supply noise in early design phases, with minimum risk and cost.
According to Teklatech founder and CEO, Dr Tobias Bjerregaard: "FloorDirector produces a 51% reduction in power peaks over baseline EDA flows from major vendors".
In today's SoC designs, dynamic power peaks are of increasing significance.
They can lead to ground and power bounces, impairing signal integrity and noise margins, and forcing conservative constraints on SoC implementation.
Voltage drops and supply noise will lead to unpredictable signal integrity, power integrity and timing effects and may cause a silicon failure.
Mixed-signal SoCs encounter additional challenges due to noise coupling between digital and analoguey parts which degrades RF performance.
The FloorDirector floorplanning engine analyses the dynamic power signature of every system block and identifies initiators of critical voltage drop chains in the design.
Using novel power shaping techniques and statistical clock timing analysis, FloorDirector provides system-level IR drop solutions while maintaining scalable clock-level synchronisation.
This allows engineers to floorplan a chip for optimal power peak flattening, leading to reduced dynamic IR drop and hence improving overall signal and power integrity.
"Teklatech is sharply focused on meeting the difficult challenges of the semiconductor industry moving into the nanometre era", adds Bjerregaard.
"We strongly believe we can drive the power/cost curve of designs at 90nm and below, enabling companies to eliminate costly silicon respins and achieve faster time to market, leading to smaller, faster and more profitable semiconductor products".
Teklatech formally unveiled its new EDA software tool at DATE show in Munich, demonstrating its benefits with real-world, MPSoC designs.
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