Pseudo-SRAM is space-saving alternative to SDRAM

As well as offering a lower power alternative to SDRAM in portable and battery-powered equipment, pseudo-SRAM devices minimise component count by eliminating the need for DRAM interface circuitry.

As well as offering a smaller, lower power alternative to SDRAM in portable and battery-powered equipment, the industry's highest density 32Mbit and world's first 64Mbit pseudo-SRAM devices also minimise component count by eliminating the need for DRAM interface circuitry.

Featuring a standard SRAM interface and single-transistor DRAM-like memory cell structure, Toshiba's 32 and 64Mbit pseudo-SRAM devices are targeted at applications such as PDAs and next-generation mobile phones.

Standby currents of just 70uA for the 32Mbit technology and 100uA for the 64Mbit devices are around half that of low-power SDRAM, while a 'deep power down' standby mode of just 5uA ensures further power savings.

In addition, because pseudo-SRAM does not use a pipeline architecture operating current is about 10mA lower than low-power SDRAM alternatives under the same data transfer conditions.

As well as reducing power consumption, pseudo-SRAM also allows component count to be reduced because it requires none of the interface circuitry used in DRAM-based designs.

Toshiba's pseudo-SRAM delivers further space reductions through an automatic refresh feature that eliminates the need for external refresh circuitry, while an address latch ensures no data loss during refresh.

The 32 and 64Mbit pseudo-SRAM is designed for use with a single power supply voltage between 2.5 and 3.3V.

Products with 1.8V I/O are also available.

Each device is supplied in a 48-ball fine pitch ball grid arrays (FBGAs) and is logic-compatible with SRAM write-enable input.

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