CMOS ASIC process shrinks down to 90nm

Toshiba Electronics Europe is now offering 90nm TC300 ASIC technology based on the Toshiba Corporation CMOS4complementary metal oxide semiconductor process.

Toshiba Electronics Europe is now offering 90nm TC300 ASIC technology based on the Toshiba Corporation CMOS4complementary metal oxide semiconductor process.

Employing 11 layers of copper wire and low-k insulating material, TC300 delivers around a 100% increase in gate integration, a 20% increase in gate speed, and a 50% reduction in power consumption, compared to the previous TC280 0.13-micron process technology.

The CMOS4 build-on-modular process permits easy mixing of mixed signal, DRAM and application specific IP on the same chip.

TC300 offers logic densities of up to 400,000 gates per square millimetre and is targeted at next-generation, high-end applications ranging from high-speed intensive networking and server applications to digital multimedia devices that manage audio/video information.

The technology will also be suitable for portable wireless devices that require low-power consumption.

Toshiba is currently the only company with 90nm embedded DRAM suitable for mass production and two types allow optimisation for speed or density.

SD type DRAM is ideal for high-bandwidth applications and has a maximum data transfer rate of 9.6Gbyte/s, FA type DRAM is optimised for fast access with a random access time of 6-8ns and a maximum I/O width of 288bit.

Both DRAM types use Toshiba's trench capacitor technology that permits the mixing of logic and DRAM processes without performance degradation.

In addition to DRAM, static random access memory (SRAM) cores support fast SRAM, high-integration SRAM, register files and high-integration read only memory.

TC300 cell libraries encompass a vast portfolio of compact, primitive cells optimised for automatic synthesis and multi-threshold voltage.

This makes it possible to select fast, ultra-fast or low-power consumption cells for the optimal design results.

Input/output (I/O) cells support high-performance serdes chip-to-chip interface applications for backplane and line card products as well as GigaEther, FibreChannel, Sonet and Firewire (IEEE1394) applications.

A rapidly growing library of application specific IP includes processor cores, memory, analogue functions and networking IP.

Toshiba's CMOS4 process has three sets of Vth transistors available and gates can be optimised for performance and/or power.

As well as the standard I/O slot options that are suitable for most designs, Toshiba can also offer a low height option for pad-limited designs.

The TC300 technology is compatible with a range of package types for high-performance SoCs, including 625- to 2304-pin flip chip ball grid array (FCBGA), 97-361 PFBGA chip scale packages, and a 256- to 648-pin PBGA package with a multilayer structure and superior electrical characteristics.

Toshiba also expects that this technology will be used for large chips incorporated with smaller mixed signal chips in small outline package (SOP) solutions.

Toshiba has developed a new, advanced EDA methodology for the TC300.

The sign-off interface uses the industry-standard Synopsys static timing analysis (STA) and standard test interface language (STIL.) These new interfaces allow greater timing precision and make it easier for fabless semiconductor companies to interface with Toshiba.

In addition, TC300 is supported by full-chip hierarchical design implementation and verification methodologies.

Toshiba has also added enhanced signal integrity and cross talk analysis tools.

This design environment supports virtually all of the industry's leading-edge tools, including the Cadence and Magma design environments.

TC300 is available for immediate design acceptance.

Mass production is targeted for the second quarter of 2003, with high-volume production expected in the third quarter of 2003.

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