Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: Toshiba Electronics Europe | Subject: Single chip H.264/MPEG-4
Edited by the Electronicstalk Editorial
Team on 17 February 2005
Mobile chip cuts power budget for H.264
Toshiba has fabricated a single chip H.264/MPEG-4 audiovisual LSI for mobile applications with a module-wise dynamic voltage/frequency scaling architecture in a 90nm 6M CMOS technology.
Toshiba has fabricated a single chip H.264/MPEG-4 audiovisual LSI for mobile applications - including terrestrial digital broadcasting systems such as ISDB-T and DVB-H - with a module-wise dynamic voltage/frequency scaling architecture in a 90nm 6M CMOS technology This LSI operates even during the voltage/frequency transition, so there is no performance overhead
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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Voltage/frequency scaling is realised by a dynamic deskewing system (DSS) and an on-chip voltage regulator with slew rate control.
H.264 and MPEG-4 standards play essential roles in the field of mobile multimedia.
H.264 is a video compression standard adopted for terrestrial digital broadcasting.
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Demands for larger image size, higher frame rate and higher image quality are ever increasing.
These demands require larger memory capacity and higher operating frequency, both resulting in higher power consumption, which is unacceptable for battery powered mobile devices.
Toshiba's LSI decodes CIF (352 x 288) H.264 baseline profile at level 2, or encodes VGA (640 x 480) MPEG-4 SP L4a video stream at 30 frames/s while encoding/decoding audio/speech streams and multiplexing/demultiplexing them at 180MHz.
The chip contains four major modules: video front end, video back end, audio/speech and multiplexer/demultiplexer.
Each of the modules consists of an optimally configured 32b media-embedded processor (MeP) core and dedicated hardware accelerators for its specific operation.
As for voltage and frequency, this chip slows down the audio module independently from the rest of the chip.
The audio module is decoupled by a voltage/frequency socket from the main bus and an on-chip voltage regulator and a dynamic deskewing system (DDS) for the dynamic voltage/frequency scaling.
The new LSI has a software controllable voltage/frequency scaling system for the audio module; therefore operating resources are minutely controlled by the resource requirement of running programs.
The power consumption for the audio element that decodes MPEG-4 AAC can be reduced by 40%.
compared with previous video standards, H.264 requires very high programmability, making it very difficult to implement in dedicated hardware accelerators.
Co-operation between the processor core and dedicated hardware accelerators have successfully reduced a large amount of operating time and power consumption without losing the programmability necessary for H.264.
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