Product category:
Memory Devices and Modules
News Release from: Toshiba Electronics Europe
Edited by the Electronicstalk Editorial
Team on 13 June 2007
3D structure offers increased Flash
density
Novel three-dimensional memory cell array structure does not rely on advances in process technology, and has minimal increase in the chip die size.
Toshiba has developed a novel three-dimensional memory cell array structure claimed to enhance both cell density and data capacity The cell does not rely on advances in process technology, and has minimal increase in the chip die size
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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Bigger Flash devices promise monster card density
Toshiba has doubled the capacity of its largest single-die NAND Flash memory lineup with the release of a 2Gbit device.
In the new structure, pillars of stacked memory elements pass vertically through multistacked layers of electrode material and utilise shared peripheral circuits.
The innovative design is a potential candidate technology for meeting future demand for higher density NAND Flash memory.
Typically, advances in memory density reflect advances in process technology.
Toshiba's new approach is based on innovations in the stacking process.
Existing memory stacking technologies simply stack two-dimensional memory array on top of another, repeating the same set of processes.
While this achieves increased memory cell density, it makes the manufacturing process longer and more complex.
The new array does increase memory cell density, is easier to fabricate, and does not produce much increase in chip area, as peripheral circuits are shared by several silicon pillars.
Toshiba's cutting edge etching technology drives a through-hole down through a stacked substrate, ie a multilayer sandwich of gate electrodes and insulator films.
Pillars of silicon lightly doped with impurities are deposited to fill in the holes.
The gate electrode wraps around the silicon pillar at even intervals, and a preformed nitride film for data retention, set in each joint, functions as a NAND cell.
NAND Flash memory functions through batch processing of cells, in large numbers of elements connected in series.
Toshiba's new array increases density without increasing chip dimension, as the number of connected elements increases in direct proportion to stack height.
For example, a 32-layer stack realises 10 times the integration of a standard chip formed with the same generation of technology.
Toshiba will further develop this elemental technology to the level where it matches current structures in terms of security and reliability.
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