Product category:
Memory Devices and Modules
News Release from: Toshiba Electronics Europe | Subject: 16Gbit NAND Flash memory
Edited by the Electronicstalk Editorial
Team on 08 February 2008
Big NAND Flash shrinks to 43nm process
New 16Gbit products have a chip area less than 70% that of same-density NAND Flash memories fabricated with 56nm process.
Toshiba and SanDisk have codeveloped technology for a 16Gbit NAND Flash memory chip fabricated using 43nm process technology The new 16Gbit products have a chip area of approximately 120mm2, less than 70% that of same-density NAND Flash memories jointly developed by Toshiba and SanDisk and fabricated with 56nm process technology
This article was originally published on Electronicstalk on 26 Jan 2007 at 8.00am (UK)
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Memory cells are grouped and controlled in NAND strings of 64 cells aligned in parallel, double the number of 56nm devices, with a dummy word-line cell at either end to prevent program disturbance.
This technology contributes to reduce the number of select gates and to improve memory area efficiency.
Modification of the peripheral circuit design also contributes to reduced chip area: the addition of high voltage switches to the circuit reduces the number of control gate driver circuits required to drive word lines, and ground buses are routed on the memory cell arrays.
Toshiba has begun sampling the new 16Gbit single-chip multilevel-cell (MLC) NAND Flash memories, the current mainstream density, and will start mass production from March.
Toshiba intends to start mass production of 32Gbit NAND Flash memories early in Q3 2008.
The new chips will be produced at Fab 4, the latest 300mm wafer fabrication facility at Toshiba's Yokkaichi Operations, in Mie prefecture, Japan.
By combining advanced process and MLC technologies, and through continued advances in production efficiency, Toshiba intends to enhance cost competitiveness and meet the needs of the NAND Flash memory market.
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