Carrier packet engine cuts consumption

The TPX3103 can provide a maximum nonblocking, full duplex switching capacity of 52Gbit/s allowing a maximum of 48x 1Gbit/s or 4x 10Gbit/s Ethernet ports.

The latest Softsilicon product from Tpack is the Smartpack TPX3103 52Gbit/s carrier packet engine.

The TPX3103 is an upgraded version of the popular TPX3100 PBB-TE/T-MPLS/VPLS carrier packet engine, which was the first commercial chip solution to offer support for all of these protocols simultaneously.

The TPX3103 is based on an Altera Stratix III FPGA, resulting in a lower power consumption of 12W per device.

Based on a mated device configuration, the TPX3103 can provide a maximum nonblocking, full duplex switching capacity of 52Gbit/s allowing a maximum of 48x 1Gbit/s or 4x 10Gbit/s Ethernet ports.

As a Softsilicon product, it is offered as a standard chip similar to an ASSP, but has the advantage of allowing rapid updates in response to changes in PBB-TE, T-MPLS and VPLS standards, which are likely to occur over the coming years.

"Due to the number of new concepts continually introduced in the emerging Carrier Ethernet segment, such as PBT (PBB-TE) and T-MPLS, OEMs are unsure which concepts will become the de-facto standard for supporting Carrier Ethernet services", says Aileen Arcilla, Principal Analyst at IDC.

"Unlike NPUs and network processing ASSPs, offering a FPGA-based solution can allow OEMs to address the flexibility in support and time to market issues associated with rapid changes in carrier Ethernet requirements".

Ideal for carrier Ethernet gateway devices, the TPX3103 provides full, proven hardware support for PBB-TE and T-MPLS OAM, allowing protection switching times well within the 50ms carrier grade specification.

This capability was demonstrated as part of the EANTC Interoperability showcase held at Carrier Ethernet World Congress 2007.

Back to top