Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: TSMC | Subject: 90nm X Architecture
Edited by the Electronicstalk Editorial
Team on 17 October 2005
X Architecture designs move down to 90nm
Taiwan Semiconductor Manufacturing Company is ready to accept 90nm X Architecture designs.
Taiwan Semiconductor Manufacturing Company is ready to accept 90nm X Architecture designs The company has successfully qualified 90nm X Architecture design rules that can enable lower cost, higher performance and lower power designs
This article was originally published on Electronicstalk on 17 Oct 2005 at 8.00am (UK)
Related stories
65nm SoC technology comes on stream
Taiwan Semiconductor Manufacturing Company has successfully completed the first of three CyberShuttle prototype production runs for the company's industry leading 65nm Nexsys technology.
Half-node process provides 19% design shrink
Taiwan Semiconductor Manufacturing Company has entered full production of its 80nm "half-node" process technology for high-performance designs.
TSMC and Cadence Design Systems have collaborated to validate the Cadence X Architecture design solution for the process.
The two companies are now engaging mutual customers.
"TSMC and Cadence have worked collaboratively on the X Architecture for multiple process generations", said Ed Wan, Senior Director of Product Marketing for TSMC's Design Services Division.
Further reading
65nm low power process is ready to roll
Earlier this week, Taiwan Semiconductor Manufacturing Company today told a packed audience at its 2006 Technology Symposium that the company has fully qualified its 65nm low power process technology.
X Architecture migrates down to 65nm
The Cadence X Architecture has been validated for TSMC's 65nm Nexsys process.
"In each case, we have demonstrated tangible benefits in at least one of three critical areas: cost, performance or power, depending on the design".
Earlier this year, ATI Technologies, Cadence and TSMC successfully produced the foundry industry's first X Architecture device - a high-performance, high-volume PCI-Express graphics processor.
ATI implemented the device using the Cadence X Architecture design solution and manufactured it on TSMC's 0.11-micron process.
The design eliminated one metal layer, reducing the device's die cost.
Cadence and TSMC are members of the X Initiative, a semiconductor design chain consortium chartered with accelerating fabrication of the X Architecture.
The X Architecture represents a new way of orienting a chip's microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle "Manhattan" routing.
The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer vias (the connectors between wiring layers).
"The combination of TSMC's advanced 90nm process technology and the Cadence X Architecture design solution provides a powerful way to optimise designs for today's challenging market needs", said Kalyan Thumaty, Vice President and General Manager of X Architecture at Cadence.
"Working closely with TSMC and leading fabless semiconductor companies, we're helping the industry adopt the X Architecture and reap the benefits of this innovative approach".
The Cadence X Architecture design solution is the industry's first physical design solution that enables the pervasive use of diagonal routes and employs the familiar netlist-to-GDSII flow.
While leveraging Cadence's industry-proven Manhattan implementation expertise, the solution draws on innovations in placement, routing, infrastructure and extraction technologies.
Cadence X Architecture design solutions for TSMC's 0.13-micron, 0.11-micron and 90nm processes are now available to customers.
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