Visit the National Instruments web site
Click on the advert above to visit the company web site

Product category: Microprocessors, Microcontrollers and DSPs
News Release from: TSMC | Subject: 80nm "half-node" process technology
Edited by the Electronicstalk Editorial Team on 20 January 2006

Half-node process provides 19% design
shrink

Request your FREE weekly copy of the Electronicstalk email newsletter. News about Microprocessors, Microcontrollers and DSPs and more every issue. Click here for details.

Taiwan Semiconductor Manufacturing Company has entered full production of its 80nm "half-node" process technology for high-performance designs.

Taiwan Semiconductor Manufacturing Company has entered full production of its 80nm "half-node" process technology for high-performance designs With this process, designers can improve performance and reduce the overall size of their designs by up to 19%, resulting in more die per wafer and more than 20% cost-per-die reduction

"TSMC offers the half-node as an extra option to our customers", said Jason Chen, Vice President of Corporate Development for TSMC.

"The potential performance, die area and yield improvements, coupled with the cost-per-die savings, provide a clear competitive advantage and easy shrink path for our customers".

"Using the latest processes brings cost and performance advantages to our graphics chips", said Rich Heye, Vice President and General Manager of Desktop, at ATI.

"Being first to 90nm gave us the lead in performance and features and moving to 80nm will improve our costs, too".

"Nvidia and TSMC have a longstanding strategic collaboration involving half-node technologies", said Chris Malachowsky, Senior Vice President of Engineering and Operations, Nvidia.

"The ability to quickly port a design to a new technology with higher performance and a smaller footprint is a powerful tool in a competitive, consumer oriented market".

The 80nm process is a lithographic shrink of the 90nm process technology.

As a consequence, this node supports most of 90nm TSMC and third-party libraries and IP requiring only simple recharacterisation using 80nm models.

Design rules are also a linear shrink from 90nm.

The result is a significantly reduced redesign time to port the chip to the new process.

TSMC has a history of success with its unique half-node strategy.

The company first began offering half-node processes at the 0.35-micron generation (with the half-step 0.30-micron), followed by the 0.25- micron (half-node 0.22), 0.18-micron (half-node 0.16), and 0.13- micron (half-node 0.11) generations.

In each case, high-volume leaders in various markets have seen significant strategic and financial advantage by employing half-node processes.

The first 80nm process in production is TSMC's high-performance GT process, which will be followed next month by the high-speed HS process and low power LP processes in March 2006.

A special GC process, which provides both low active and standby power advantage, will become available in the third quarter of 2006.

TSMC: contact details and other news
Email this article to a colleague
Register for the free Electronicstalk email newsletter
Electronicstalk Home Page

Search the Pro-Talk network of sites

Visit the National Instruments web site