Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: TSMC
Edited by the Electronicstalk Editorial
Team on 24 February 2006
Immersion lithography passes the test
TSMC has revealed that its immersion lithography programme has produced test wafers well within acceptable parameters for volume manufacturing.
TSMC has revealed that its immersion lithography programme has produced test wafers well within acceptable parameters for volume manufacturing The findings, to be revealed by TSMC researchers at the SPIE Microlithography Conference in San Jose, prove the value of TSMC's proprietary techniques for nearly defect- free immersion lithography
This article was originally published on Electronicstalk on 17 Oct 2005 at 8.00am (UK)
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"Our goal is always zero defects", said Burn Lin, Senior Director of TSMC's Micropatterning Division and a recognised immersion lithography expert.
"Recently, TSMC produced multiple test wafers with defects rates as low as three per wafer - better than any other immersion results to date, and comparable to the very best dry lithography results".
"With defect root causes understood, TSMC can now focus on throughput improvement for high-volume manufacturing".
Immersion techniques extend the useful life of current-generation lithography systems, the large, multi-million-dollar, camera-like machines that are the heart of semiconductor manufacturing.
The ability to extend the usefulness of these machines is considered crucial to enabling future generations of semiconductor manufacturing, as alternative lithography systems are much further from production-worthiness.
Immersion lithography systems use water, or a similar clear liquid, as an image-coupling medium.
By placing water between the lithographic lens and the semiconductor, engineers can preserve higher-resolution light from the lens, enabling smaller, more densely- packed devices.
But liquid media present their own challenges, including defects such as bubbles, watermarks, particles, particle-induced printing defects and resist residue.
TSMC's R and D researchers resolved these issues by developing a proprietary defect-reduction technique that, on initial tests, produced less than seven immersion-induced defects on many 12in wafers, a defect density of 0.014/cm2.
Some wafers have yielded defects as low as three per wafer, or 0.006/cm2.
This compares with several hundred thousand defects produced by a prototype immersion scanner without these proprietary techniques and significantly better than published champion data in double digits.
TSMC's immersion lithography technology is targeted at TSMC's 45nm manufacturing process.
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