Design for manufacturing tools support 65nm node

A 65nm design support ecosystem channels design-for-manufacturing capabilities through selected electronic design automation tools directly to designers' workstations.

Taiwan Semiconductor Manufacturing Company has unveiled an extensive 65nm DFM compliance design support ecosystem that's driven by a manufacturing-based unified data format to channel design-for-manufacturing (DFM) capabilities through selected electronic design automation (EDA) tools directly to designers' workstations.

TSMC developed the unified format to align DFM tools - lithography process check (LPC), chemical mechanical polishing (CMP) analysis and critical area analysis (CAA) - to TSMC's manufacturing data format.

This allows designers to use the same DFM data file irrespective of the tool or vendor.

It also enables simplified use, management and updates to DFM analyses using these tools.

Designers can download an encrypted TSMC DFM data kit (DDK), compiled in the DUF format, and run TSMC-qualified DFM tools directly on their workstations, with results that are consistent with the company's own internal DFM results.

The ecosystem results from a year-long collaboration between TSMC and its design partners to shorten the 65nm design cycle and reduce time to volume and time to market for leading-edge products.

"This is a comprehensive collaboration to deliver 65nm DFM-compliant products and design services to the designer's desktop", said Edward Wan, Senior Director of Design Services Marketing for TSMC.

"Basically, we've defined what it means to be DFM compliant, and we've helped our ecosystem partners to achieve that compliance".

The TSMC 65nm design support ecosystem defines a DFM-compliant IC design infrastructure.

By aggressively driving its process knowledge up the design chain, TSMC and its design service alliance partners improve 65nm design quality.

TSMC worked with a select number of third-party EDA vendors to qualify their tools.

The qualification ensures that the results from the tools are consistent with those from TSMC's own internal results.

Run-time performance and user-friendliness are also essential parts of this qualification procedure.

This qualification procedure involves tools from Anchor Semiconductor, Cadence Design Systems, Clear Shape Technologies, Magma Design Automation, Mentor Graphics, Ponte Solutions, Predictions Software and Synopsys.

TSMC has defined the industry's first set of IP and library compliance criteria which includes running checks, such as DFM layout parasitic extraction (LPE), a layout enhancer, and lithography process check (LPC), using TSMC's DFM database to achieve optimal DFM results in terms of timing accuracy and hot-spot removal.

Through an intensive training program, the company assists third-party IP and library vendors to achieve this DFM compliance.

TSMC has worked with an initial set of DCA members to hone their ability to implement 65nm DFM-compliant design practices.

Some DCA partners have already helped 65nm early adopters to achieve successful tape outs.

Today, the DFM-compliance initiative encompasses 18 companies from the IP, library, EDA and design centre communities, including: Alchip, Anchor, Aprio, AnalogBits, ARM, Blaze DFM, Cadence, Clear Shape, Dolphin Technology, Fastrack, Global Unichip, Magma, Mentor, Ponte, Predictions, Qthink, Synopsys and Virage Logic.

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