Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: TSMC | Subject: 65nm low power process
Edited by the Electronicstalk Editorial
Team on 19 May 2006
65nm low power process is ready to roll
Earlier this week, Taiwan Semiconductor Manufacturing Company today told a packed audience at its 2006 Technology Symposium that the company has fully qualified its 65nm low power process technology.
Earlier this week, Taiwan Semiconductor Manufacturing Company today told a packed audience at its 2006 Technology Symposium that the company has fully qualified its 65nm low power process technology The announcement officially opens the doors for TSMC to deliver the production-ready 65nm process
This article was originally published on Electronicstalk on 13 Jun 2008 at 8.00am (UK)
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With several products already ramped and delivering production volumes, the new process provides higher levels of integration and performance improvement with groundbreaking power management technology for the lowest possible power usage.
The new 65nm process is supported by TSMC's Design Support Ecosystem, featuring DFM-compliant 65nm products and services; by TSMC's Reference Flow 6.0 design methodology; and by a variety of process-proven TSMC and third-party libraries and IP.
"TSMC again leads the industry in pushing Moore's law to the 65 nanometre generation", said Dr Rick Tsai, President and Chief Executive Officer, TSMC.
"At 65nm geometries, we can produce highly integrated, very small and low power devices for every conceivable market".
"Producing on our advanced 300mm wafers, we can ramp customer's design to high volume quickly".
"It provides unprecedented opportunities for customers to further advance the leadership positions in their marketplaces".
TSMC's 65nm Nexsys technology is the company's third-generation semiconductor process employing both copper interconnects and low-k dielectrics.
It is a nine-layer metal process with core voltages of 1.0 or 1.2V, and I/O voltages of 1.8, 2.5 or 3.3V.
The new technology offering supports a standard cell gate density twice that of TSMC's 90nm Nexsys process.
It also features very competitive 6T SRAM and 1T embedded DRAM cell sizes.
In addition, this technology offering includes mixed signal and radio frequency functionality to support analogue and wireless design, embedded high density memory to support integration of logic and memory, and electrical fuse to support customer encryption needs.
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