Product category:
Memory Devices and Modules
News Release from: TSMC | Subject: 65nm process for embedded DRAMs
Edited by the Electronicstalk Editorial
Team on 08 March 2007
New 65nm process for embedded DRAMs
A new 65nm embedded DRAM process and IP provide a higher bandwidth, lower power consumption, and a close to 50% smaller cell and macro size than previous high density memory generations
Taiwan Semiconductor has announced a 65nm embedded DRAM process The TSMC foundry achieved 65nm product production in the second quarter last year and has also been producing 90nm embedded DRAM products since the first quarter of 2006
This article was originally published on Electronicstalk on 17 Oct 2005 at 8.00am (UK)
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X Architecture designs move down to 90nm
Taiwan Semiconductor Manufacturing Company is ready to accept 90nm X Architecture designs.
65nm SoC technology comes on stream
Taiwan Semiconductor Manufacturing Company has successfully completed the first of three CyberShuttle prototype production runs for the company's industry leading 65nm Nexsys technology.
Memory macros, developed by TSMC's design team, are currently being used in more than a dozen 90nm customer products.
TSMC's 65nm embedded DRAM process and IP provide a higher bandwidth, lower power consumption, and a close to 50% smaller cell and macro size than previous high density memory generations.
"Nvidia is pleased to have collaborated with TSMC on its new 65nm embedded DRAM process, which has proven to be an excellent platform for our latest handheld GPU product", says Michael Rayfield, General Manager of the Handheld Division of Nvidia Corporation.
Further reading
Half-node process provides 19% design shrink
Taiwan Semiconductor Manufacturing Company has entered full production of its 80nm "half-node" process technology for high-performance designs.
65nm low power process is ready to roll
Earlier this week, Taiwan Semiconductor Manufacturing Company today told a packed audience at its 2006 Technology Symposium that the company has fully qualified its 65nm low power process technology.
"The efficiencies of the embedded DRAM process allowed us to raise the bar for features found in mainstream cell phones".
"We've talked to customers and understand their needs".
"TSMC firmly believes that this new embedded DRAM process and IP are well suited for the demands created by the convergence of the wireless, consumer and communications devices".
"The results will be multifunctional computing platform that will spawn the next generation of innovation", says Jason Chen, Vice President of Corporate Development, TSMC.
The 65nm embedded DRAM's higher bandwidth is suitable for game console, high-end networking, digital consumer, and multimedia processors.
It consumes less active and stand-by power than alternative high-density memory technology while eliminating the need to power up I/Os.
TSMC 65nm embedded DRAM's flexibility supports product designs with a smaller form factor by enabling both logic and memory functions to be built on a single device thus saving board space and enhancing systems reliability.
TSMC 65nm embedded DRAM uses a low thermal budget module that can be added to the company's standard CMOS process.
It is compatible with all 65nm logic libraries making it an efficient process for IP reuse.
The embedded DRAM design features improved retention time and special power saving options for low power applications including sleep mode, partial power cut-off and on-chip temperature compensation.
The 65nm embedded DRAM process is built on up to 10 metal layers using copper low-k interconnect and nickel silicide transistor interconnect.
It has a cell size less than a quarter of its SRAM counterpart, and macro densities ranging from 4 to 256Mbit.
Both the 65nm embedded DRAM and IP are supported by TSMC's Design Support Ecosystem with DFM-compliant 65nm products and services; by TSMC's Reference Flow 7.0 design methodology; and by a variety of process-proven TSMC and third party IP and libraries including SRAM compilers, I/Os and standard cell libraries.
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