Foundry offers support services for 45nm process

A full range of design support services for foundry's 45nm process includes prototyping

Taiwan Semiconductor Manufacturing Company (TSMC) has announced a full range of design support services for its 45nm process.

TSMC's 45nm production will start from September of this year.

Designed to accelerate the adoption of new technologies, TSMC's design ecosystem offers the foundry industry's largest portfolio of process-proven libraries and IP, design tools and reference flows.

TSMC's prototyping programs streamline the transition from first silicon to production, including the QuickStartSM IP program, the Prototype Diagnostics Alliance and CyberShuttleSM.

CyberShuttle allows multiple customers to share the costs of a single mask set and prototype wafers on a pilot run.

TSMC's 45nm design ecosystem includes the industry's most advanced technology libraries, including standard cell, standard I/O, single-port SRAM, dual-port SRAM and more.

The Library Alliance Program supports TSMC's extensive portfolio of silicon-proven third-party IP.

TSMC 45nm PDKs cover the entire design flow from schematic entry, simulation, layout, and layout check to post-simulation.

The 6-stage automatic PDK quality assurance flow with over 133 procedures ensures consistent quality control and faster development lead time.

Adoption is simplified with smart installation and tutorial, and design accuracy is improved with support for well proximity effect (WPE) modeling, Monte Carlo simulation, and estimated parasitic RC device information for pre-simulation.

TSMC's 45nm initiative goes beyond traditionally supplied design rules and Spice models, providing additional manufacturing variance data that is essential for achieving high yields at the nanometer level.

A model-based approach and a rule-based approach are available for designer implementation, with a DFM Data Kit (DDK) for third-party EDA tools and a TSMC DFM toolkit with advisories and utilities.

TSMC also provides extensive in-house services that enable reliable, rapid tape-out and production, along with comprehensive backend services from CP test to drop-shipping.

TSMC's 45nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material.

With an exceptionally high gate density and high-density 6T SRAM cell, more than 500 million transistors will easily fit into a 70mm2 die area.

TSMC's low-power 45nm process is expected to be available first, followed soon after by the general purpose and high-performance process.

In addition, the 45nm logic family includes a low-power triple gate oxide (LPG) option.

All three processes offer multiple threshold voltage (Vt) core devices and 1.8, 2.5 and 3.3V I/O options to meet different product requirements.

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