Mixed-signal process runs on 32nm node

Leading edge technology is optimised for low power, high density and manufacturing margins with optimal process complexity and cost management.

Taiwan Semiconductor Manufacturing Company has developed the first 32nm technology that supports both analogue and digital functionality.

The company made its announcement through a paper presented at the IEEE International Electron Devices Meeting in Washington, DC.

The paper also revealed that the company had proved the full functionality of the 2Mbit SRAM test chip with the smallest bit-cell at the 32nm node.

This leading edge technology is optimised for low power, high density and manufacturing margins with optimal process complexity and cost management.

Low power technology integrated with high density SRAM, low standby transistors, analogue and RF functions, and copper and low-k interconnects is ideal for system on chip (SoC) devices targeted in mobile applications.

TSMC plans to provide complete digital, analogue and RF functions, and high density memory capabilities at 32nm node.

Noteworthy in the announcement is the fact that this is the first 32nm low-power technology that did not have to resort to high-cost high-k gate dielectric and metal gates to achieve its performance characteristics.

In addition, a 0.15um2 high density SRAM cell has been realised by 193nm immersion lithography using double patterning approach.

"With this announcement, TSMC continues to lead the industry by pushing the boundaries of advanced technology", said Dr Jack Sun, Vice President R and D, TSMC.

"The achievement made at 32nm technology node is yet another testimony to our long-term investment and commitment in advanced technology development to help our customers in bringing their leading-edge products first to market".

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