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Electronics Manufacturing Services
News Release from: TSMC | Subject: 40G and LP processes
Edited by the Electronicstalk Editorial
Team on 25 March 2008
Manufacturing processes shrink to 40nm
Options include 40LP for leakage-sensitive applications such as wireless and portable devices and 40G for performance applications including CPUs, GPUs and FPGAs.
Taiwan Semiconductor Manufacturing Company has unveiled its first 40nm manufacturing process technology The new node supports a performance-driven general purpose (40G) technology and a power-efficient low power (40LP) technology
This article was originally published on Electronicstalk on 17 Oct 2005 at 8.00am (UK)
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Taiwan Semiconductor Manufacturing Company is ready to accept 90nm X Architecture designs.
65nm SoC technology comes on stream
Taiwan Semiconductor Manufacturing Company has successfully completed the first of three CyberShuttle prototype production runs for the company's industry leading 65nm Nexsys technology.
It features a full design service package and a design ecosystem that covers verified third party IP, third party EDA tools, TSMC-generated Spice models and foundation IPs.
First wafers out are expected in the second quarter of 2008.
Following successful tapeouts and customer announcements of its 45nm process technology in 2007, TSMC has moved forward quickly and developed an enhanced 40LP and 40G process that delivers industry-leading performance with 40nm density.
Further reading
Half-node process provides 19% design shrink
Taiwan Semiconductor Manufacturing Company has entered full production of its 80nm "half-node" process technology for high-performance designs.
65nm low power process is ready to roll
Earlier this week, Taiwan Semiconductor Manufacturing Company today told a packed audience at its 2006 Technology Symposium that the company has fully qualified its 65nm low power process technology.
The 45nm node provided double the gate density of 65nm, and the new 40nm node features manufacturing innovations that enable its LP and G processes to deliver a 2.35 raw gate density improvement of the 65nm offering.
The transition from 45 to 40nm low power technology reduces power scaling up to 15%.
"Our design flow can take designs started at 45nm and target it toward the advantages of 40nm", says John Wei, Senior Director of Advanced Technology Marketing at TSMC.
"A lot of TSMC development work has gone into ensuring that this transition is truly transparent".
"Designers need only concentrate on achieving their performance objectives", he said.
TSMC has developed the 40LP for leakage-sensitive applications such as wireless and portable devices and its 40G variant targeting performance applications including CPU, GPU (graphic processing unit), game console, networking and FPGA designs and other high-performance consumer devices.
The 40nm footprint is linearly shrunk and the SRAM performance is fully maintained when compared with its 45nm counterpart, its SRAM cell size is now the smallest in the industry at 0.242um2.
A full range of mixed signal and RF options accompany the 40G and 40LP processes along with embedded DRAM, to match the breath of applications that can take advantage of the new node's unbeatable size and performance combination.
The 40nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material.
The logic family includes a low-power triple gate oxide (LPG) option to support high performance wireless and portable applications.
Both the G and the LP processes offer multiple Vt core devices, with 1.8 and 2.5V I/O options to meet different product requirements.
TSMC's CyberShuttle prototyping service can be booked for 40nm designs in April, June, August, October and December this year and first wave 45/40nm customers have already used above 200 blocks on completed multiproject wafer runs.
The 40G and LP processes will initially run in TSMC's 12in wafer Fab 12, and will be transferred to Fab 14 as demand ramps.
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