RSS News Feed for True Circuits - from Electronicstalk http://www.electronicstalk.com/news/tue/tue000.html True Circuits news releases on Electronicstalk en-gb Copyright (C)2008 Pro-Talk Ltd. All rights reserved. Sat, 22 Nov 2008 08:00:00 UT Sat, 22 Nov 2008 08:00:00 UT Pro-Talk Ltd http://www.pro-talk.com/images/protalklogo90.gif http://www.pro-talk.com/ 90 79 Line of 65nm timing IP planned for 2007 True Circuits has announced a new line of silicon-proven TSMC 65nm phase-locked loop (PLL) and delay-locked loop (DLL) hard macros targeting high-speed timing applications. Wed, 06 Dec 2006 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue108.html Soft modem chip integrates many PLLs Multiple PLL hard macros have been used by fabless semiconductor company Icera in the Livanto ICE8020 wireless soft modem IC for 3G mobile phone and wireless devices. Tue, 25 Apr 2006 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue107.html PLL hard macros save die space A new line of phase-locked loop (PLL) hard macros from True Circuits occupy just one-third the die size of the company's current standard PLL products. Tue, 13 Jul 2004 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue106.html Wireless network processor applies multiple PLLs Ubicom has successfully implemented multiple True Circuits PLL hard macros in its IP3023T wireless network processor using TSMC's 130nm process technology. Tue, 23 Mar 2004 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue105.html Low-jitter hard macro wins key timing spot Parama Networks has implemented a True Circuits clock generator PLL as the primary clocking macro in its new ADM-on-a-Chip, fabricated in UMC's 130nm process technology. Fri, 23 Jan 2004 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue104.html PLL aids high-speed interface NEC Electronics has implemented a True Circuits clock generator PLL in a new SPI-4.2 interface hard macro fabricated in NEC's 130nm process technology. Fri, 31 Oct 2003 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue103.html Low-jitter DLL macros target DDR interfaces A new line of delay-locked loop analogue hard macros is aimed at high-speed, DDR-style interface applications. Wed, 15 Oct 2003 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue102.html Phase locked loop IP cuts down jitter True Circuits has developed a line of spread-spectrum and low-bandwidth phase-locked loop analogue hard macros with LockNow! technology. Wed, 14 May 2003 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue101.html PLL IP aids digital TV SoC The TeraLogic Group of Oak Technology is to use low-jitter PLL intellectual property from True Circuits in its Generation9 SoC, one of the industry's most advanced digital TV solutions. Tue, 19 Nov 2002 08:00:00 UT True Circuits http://www.electronicstalk.com/news/tue/tue100.html