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News Release from: True Circuits | Subject: Clock generator PLL
Edited by the Electronicstalk Editorial
Team on 31 October 2003
PLL aids high-speed interface
NEC Electronics has implemented a True Circuits clock generator PLL in a new SPI-4.2 interface hard macro fabricated in NEC's 130nm process technology.
NEC Electronics has implemented a True Circuits clock generator PLL in a new SPI-4.2 interface hard macro fabricated in NEC's 130nm process technology "We selected True Circuits' clock generator PLL for this high-speed communications application because of its small size, wide frequency range and superior low-jitter performance", said Hideya Horikawa, Senior Design Engineering Manager, NEC Electronics America
This article was originally published on Electronicstalk on 23 Jan 2004 at 8.00am (UK)
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Low-jitter hard macro wins key timing spot
Parama Networks has implemented a True Circuits clock generator PLL as the primary clocking macro in its new ADM-on-a-Chip, fabricated in UMC's 130nm process technology.
"The performance of the TCI PLL will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10Gbit/s Sonet/SDH systems".
"Our clock generator PLL hard macros are very flexible, have wide frequency and multiplication ranges, and produce optimal jitter performance over all multiplication settings", noted Dr John G Maneatis, President of True Circuits.
"These design characteristics were particularly important for this high-speed interface application and we are proud to bring this timing flexibility and performance to NEC Electronics and their many ASIC customers".
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