Product category:
Communications ICs (Wired)
News Release from: Tundra Semiconductor
Edited by the Electronicstalk Editorial
Team on 14 October 2002
RapidIO to be demonstrated at
Electronica
Tundra Semiconductor will be demonstrating the RapidIO hardware interoperability platform (HIP) at Electronica next month in Munich.
Tundra Semiconductor will be demonstrating the RapidIO hardware interoperability platform (HIP) at Electronica next month in Munich The HIP has been developed to support multivendor silicon interoperability testing - a key step in enabling RapidIO
This article was originally published on Electronicstalk on 25 May 2001 at 8.00am (UK)
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The HIP demonstration is an example of the ease in which three independent vendors can work successfully together with the emerging RapidIO standard.
The platform consists of the Tundra HIP motherboard supported by two Altera plug-in boards supporting its new Stratix FPGA device family and a Tektronix logic analyser differential probe interface, which communicate to each other through a predefined RapidIO interface.
Tundra will be on the Atlantik stand in Hall A4, stand 39.
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Platform to accelerate RapidIO deployment
A new hardware interoperability platform (HIP) motherboard will allow designers to evaluate RapidIO system interconnect devices from Tundra Semiconductor.
RapidIO interfaces hit the ground running
The Tsi400 RapidIO to PCI-X bus bridge and the Tsi500 RapidIO multiport switch are the first commercially available RapidIO system interconnect products.
"As the first of many to come, this HIP is both unique and powerful in its simplicity, flexibility and interoperability - this is what makes it key in the enablement of the RapidIO standard", explained Jim Parisien, Manager, Third Party Partners at Tundra.
"In order for communications infrastructure vendors to adopt RapidIO they need to see it working.
This platform provides the foundation for semiconductor, connector, diagnostic tool, software, backplane vendors, system architects and designers to build upon.
It allows diagnostic tool vendors to support one common prototyping environment.
Software vendors can begin to develop for the types of system level architectures they will support in the coming months as the processor vendors bring their products to market".
The platform will demonstrate video over RapidIO.
A DVD player acts as the video source, which is digitised and then processed into RapidIO packets by the Altera Stratix FPGA within the first Altera plug-in card.
This video stream then flows over the Tundra RapidIO motherboard through a non-invasive in-line Tektronix logic analyser probe and on to the second Altera plug-in card.
The second plug-in card extracts the video information from the RapidIO packet payload, converts it back into an analogue format and displays it on a TV monitor.
Altera represents the first silicon vendor demonstrating the first stage of interoperability testing from one plug-in card to another.
The Tektronix logic analyser shows the key value of a highly capable RapidIO diagnostic tool.
It is able to correlate digital to analogue data as well as perform disassemble functions abstracting the engineer to a higher level of system diagnostics at the packet level.
The two primary forms of HIP motherboard are switched and nonswitched.
The nonswitched motherboard (HIP1) contains no active RapidIO switch fabric.
The first pair of the four available RapidIO interfaces is routed directly together, as are the second pair.
This permits each pair of cards to communicate directly to each other achieving the first stage of interoperability testing.
The switched motherboard (HIP2) contains an active RapidIO switch fabric which can interconnect all four RapidIO slots as well as support a number of additional interconnect technologies specific to the motherboard vendor.
This permits legacy hardware and software as well as new RapidIO based hardware to be integrated completing the second stage of interoperability testing.
A Tundra version of this motherboard will be used for software development, and prototyping of larger system architectures and applications as well.
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