Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: Texas Instruments (April 2006-) | Subject: TMS320C6452
Edited by the Electronicstalk Editorial
Team on 04 October 2007
DSP boosts channel density
Digital signal processor is designed to optimise price and performance for process intensive multichannel infrastructure and medical imaging systems.
Designers of telecomms access infrastructure equipment can now double the number of VoIP and conferencing channels per dollar, lowering system cost and power while boosting overall performance The high-performance cost-effective TMS320C6452 digital signal processor (DSP) is designed to optimise price and performance for process intensive multichannel infrastructure and medical imaging systems
This article was originally published on Electronicstalk on 4 Apr 2006 at 8.00am (UK)
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Simultaneously, TI has strengthened its performance leadership position by announcing that the TMS320C6455 DSP at 1.2GHz is the world's fastest single core DSP.
"Over the years, TI's C6000T DSP platform has proven to be reliable, cost effective and easy to use", says Simon Chouldjian, VP of Hardware Engineering, AltiGen.
"TI continually improves its C6000 DSPs with higher speeds and more efficient instruction sets".
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"With the high-performance products and great support AltiGen has received during the product development lifecycle, it is easy to see why we are committed to leveraging TI's roadmap".
With a more than 30% price reduction over TI's popular TMS320C6415T DSPs, the new code compatible 900MHz C6452 DSP allows designers to quickly and easily migrate their designs from the widely deployed C641x based products.
Therefore, this broad base of customers can benefit from the advanced communications peripherals, expanded memory, heightened performance and cost benefits of the new C6452 device.
Based on TI's enhanced TMS320C64x+ core, the C6452 DSP delivers double the L1 cache memory and 40% more L2 cache than the C6415, giving customers more headroom to easily add differentiating features to their designs.
The C6452 DSP also includes two gigabit Ethernet MAC ports and one gigabit switch, which greatly improves the efficiency of multichip designs by automatically monitoring the data stream to ensure that only the appropriate packets consume DSP performance.
Additionally, the device is equipped with a Telecom Serial Interface Port (TSIP), providing a seamless connection to common telecom serial data streams, ultimately improving performance while increasing robustness and flexibility.
Increasing channel density is critical for infrastructure designs since, in most instances, rack space is fixed.
The C6452 DSP's 900MHz clock rate, expanded memory, advanced peripherals and ability to be easily daisy-chained using the two SGMII (Serial Gigabit Media Independent Interface) ports gives system-level designers the building blocks needed to increase channel density.
The C6452 DSP's lower price compared with the C6415T DSP, plus system software from third parties such as Adaptive Digital Technologies, enables twice the channels per dollar for echo cancellation, conferencing and VoIP/G.PAK applications.
The C6452 DSP has two SGMII Ethernet MAC ports and a gigabit switch to enable each individual DSP in the system to process only those packets associated with that DSP's function.
The SGMII is a widely used technology for connecting high-speed Ethernet devices at the MAC level.
TI's switch adds a decision gate that can, for example, be used to distinguish between voice and data traffic.
If a specific DSP on the card is dedicated entirely to voice processing, it blocks data traffic from entering, which makes much more effective use of its processing bandwidth.
The C6452 DSP's 66-MHz PCI interface has double the datarate.
Similarly, the DDR2 interface doubles the external memory bandwidth.
L1 instruction and data caches are doubled to 32Kbyte.
There is a 40% increase in the L2 cache size.
TI is committed to investing in its high performance roadmap and is expanding its DSP portfolio with the introduction of its 1.2GHz TMS320C6455 DSP.
The C6455 at 1.2GHz is available at the previous 1GHz price, giving developers a significant performance boost at no additional cost.
The results of Berkeley Design Technology's (BDTI) benchmark analysis of the C6455 device placed it atop all other single core programmable DSPs for speed with a BDTImark2000 score of 13170.
Because BDTI Benchmarks measure performance on a collection of algorithms, they provide performance expectations for real-world applications and are the most widely used digital signal processing benchmarks in the world.
For the most processing-intensive applications requiring the highest performance and processor-to-processor communication, the C6455 DSP combines high bandwidth peripheral integration (gigabit Ethernet MAC), Serial RapidIO (sRIO) and increased memory (2Mbyte of L2 memory) into one single device.
Customers can now place orders for the TMS320C6452 DSP, starting at US $94 at 720MHz in 10,000-unit quantities from TI.
The highly integrated device is packaged in a 19 x 19mm, 361-lead BGA (ball grid array) package.
Order entry is also open for the C6452 DSP evaluation module, priced at US $1295.
The 1.2GHz C6455 DSP is now available for $245 in 10,000-unit quantities from TI.
Order entry is open for the 1.2GHz C6455 DSP starter kit priced at $495.
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